Most current systems-on-chip (SoC) methodologies involve the selection and integration of existing internal or third-party IP blocks into a multimillion-gate design. Signal integrity between blocks has become increasingly important with semiconductor process scaling, leading to many complex modeling, design and design flow issues.

In response, the Virtual Socket Interface Alliance has created a signal integrity specification that defines the information transfer requirements between the virtual-component provider and the SoC integrator with respect to such effects.

One of the biggest concerns is interconnect crosstalk, which is usually due to the capacitive coupling between the "victim" net and one or more "aggressor" nets, although inductive coupling is also beginning to show up in cutting-edge custom designs. Interconnect delays can show up on a victim net because of noise on an adjacent aggressor net.

Capacitive crosstalk is manifested either as a degradation of interconnect speeds, resulting in a lowered operating frequency for the chip, or in outright failure of the chip. When two neighboring signals change simultaneously, they can affect each other's slew rate depending on their transition directions, relative driver strengths and wire parasitics. Thus, two signals changing in the same direction will tend to speed each other up, whereas two signals changing in opposite directions will slow each other down.

Speed degradation on critical nets can lower the operating frequency of the chip appreciably. In contrast, a failure is caused by the voltage pulse induced on a quiet victim net when one or more aggressor nets switch in its neighborhood.

Interconnect crosstalk is worsening with each process generation because of nonideal scaling of wires. Since wires grow relatively narrower and taller with each generation (in order to keep their resistance manageable), the ratio of the coupling capacitance of a wire to its total capacitance is rising with each generation. Although the move from aluminum to copper can halt that deterioration for a generation, successive generations will again have to tackle the same issues. It is becoming increasingly important to account for coupling during timing analysis.

The trend toward increasing design size and power consumption and decreasing supply voltage (thereby increasing current) magnifies the amount of power grid IR drop and ground bounce on chips. That trend is critical, since IR drop and ground bounce noise margins are decreasing along with supply voltage.

In many designs, the approach is to overdesign the power grid of the chip at the cost of metal consumption, which would otherwise be used for signal routing. The challenge facing designers is in determining how much of a power grid is actually overdesign, especially if there is no testing of the grid.

When components of a design do not see the specified power rail voltage, functional or timing failures will result. Functional failures result from insufficient power for the component to operate properly. Timing failures result from gate delays' increasing beyond the timing requirements of the paths.

Traditional digital chip testers do not test at speed or have power/ground connections equivalent to the packaged parts. As a result, they rarely catch signal-integrity-induced faults, which then manifest themselves as intermittent failures.

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