The two endpoints in the power chain are the load and the wall power plug. There is a massive proliferation of power supplies in between. The load end of the chain is in constant evolution, driven ultimately by Moore's law. The doubling of the number of transistors per given area every 18 months creates a technology hierarchy by which the CPU-at the top of the food chain-is designed with the smallest minimum feature (today, 90 nanometers) and requires the lowest supply voltages (1 to 1.5 volts).

Consequently, the previous-generation fab infrastructure at 130 nm gets recycled down the food chain for the next high-protein product-say, memories-which gets powered at voltages around 2.5 V or lower. This cycle goes on and on. The end result is a downward proliferation of power supply voltages from the old 5 V down to 3.3 V, 2.5 V, 1.5 V and so on. Since the performance of such loads (such as CPUs, memories or chip sets) tends to go up while voltage is going down, the result is an increase in power (watts) demand.

When such a load, say a CPU, is part of a computing system, it gets powered by a voltage regulator, which is typically referred to as a voltage regulator module (VRM) if the power supply is a module plugging into a socket on the motherboard. Or a voltage regulator down (VRD) powers it if the same circuitry is built in permanently "down" on the motherboard. When the same load is part of a communications system, it will be powered essentially by the same regulation electronics, now called the point of load (POL) regulator or simply POL.

On the wall-power side are two different power distribution systems, the 48-V power for telecom systems and the ac line (110 V or 220 Vac) for computing.

Traditionally, telecom systems have distributed dc power (-48 V typically) obtained from a battery backup being continually charged by a rectifier/charger from the ac line. This is the case, for example, for the power distribution in land telephones. Subsequently, this 48 V (in reality a voltage spreading from 36 V to 72 V) is converted into various low-positive dc voltages. (The figure shows 12 V only for simplicity). This downconversion generally is accomplished with isolated dc/dc converters referred to as "bricks," although nonisolated buck converters can be used in telecom applications.

Isolation in bricks is driven by a number of technical factors. These include cleaner ground loops, and easier handling of the wide input-to-output voltage ratios (easily 10:1) by means of the transformer turn ratio. And there's inherently good overvoltage protection of the load due to the low voltage at the output of the transformer. Such a 12-V (or 5-V) bus may then be reduced down to the final voltage rails (3.3 V, 2.5 V, 1.2 V, etc.) by means of a dc/dc converter for each rail or even one for each single load, depending on the overall power-management scheme. This type of low-voltage dc/dc converter is called point of load in telecom systems.

Computing power distribution

In a typical computing system (see figure) such as the PC, the power is drawn from the ac line. After rectification (ac to unregulated dc voltage conversion), the high-input voltage is bucked down to the standard 12-, 5- and 3.3-V buses by the power-factor correction and pulse-width modulation block. The "silver box" inside the PC box performs this downconversion. A cable to the motherboard delivers these voltages, where VRMs, VRDs and other flavors of voltage regulators reduce them down to the final voltage rails.

POLs and VRMs are essentially modules and come in multiple form factors. Standardization and modularization differentiate these elements and make them specific to the application at hand, but at their heart, they are powered by similar technologies and architectures. Their similarity derives from the fact that they are powering similar or identical loads from similar or identical input voltages.

The most popular architecture for step-down regulators, from 12 V or below to any voltage down to 1 V or less, is the nonisolated, multiphase interleaved buck converter.

The buck converter is a resilient architecture, thanks to its simplicity and effectiveness. Interleaved multiphase has given this architecture a new lease on life. Multiphase refers to paralleling of two or more buck converters, and interleave is the time spacing of the clock cycles between the converters.

Ripple current

As an example, two clocks in phase opposition are generated at the output of a D flip-flop, starting from a master clock. The currents in the two slices are summed to produce a total ripple current. The interleave produces these fundamental benefits:

• Effective operation at twice the single-slice frequency without the switching losses associated with high frequency of operation.
• Smaller output ripple. This architecture allows you to maintain a specified ripple with smaller output components (inductors, capacitors).
• Higher duty cycle and higher "on" time. Higher on time means lower peak currents within a clock cycle. Since the on time is the time during which current is drawn from the input capacitors, lower peak currents lead to a savings in input capacitors as well.

An issue that needs attention is phase-current balancing, or the need to ensure that all phases carry identical amounts of current. This can be accomplished in many ways-from simple ballast schemes to active current sensing and balancing.

Convergence of computing and communications is uniting two separate power universes, each with its own language, systems and classifications. Power distribution at the source starts very differently for the two, but at the POL there is clear convergence. Below the surface of VRMs and POLs, the same technologies and architectures are at play, with the interleaved buck converter between them.

Reno Rossetti is director of corporate strategy for computing at Fairchild Semiconductor International (San Jose, Calif.).

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