At the most recent ICCAD conference in Santa Clara, Calif., low-power design was a main topic of discussion at almost every panel and session. Users criticized the design automation industry for moving too slowly in creating viable tools. But EDA vendors such as Cadence, Sequence and Synopsys do offer tools for low-power design and all suppliers report that more help is on the way from the EDA industry.

In the meantime, designers are using several strategies to help deal with the issues of low-power design. In this focus report, EDA and semiconductor vendors as well as designers report on some of these methodologies, tips and tricks. Gerry Frenkil from Sequence Design Inc. outlines the low-power design problem and discusses his company's power-management integrity tool flow. Four Synopsys Inc. authors describe that company's partnership with ARM, Artisan Components and National Semiconductor on the design of power-saving intellectual property and systems-on-chip that reduce dynamic power consumption based on application software workload, available silicon performance and environmental conditions.

Jeremy Brumitt and Cameron Fisher of Virage Logic Corp. tell how to deal with power dissipation in embedded SRAMs. Russell David shows how his group at ClearSpeed Technology Inc. managed power in developing the CS301, a floating-point processor that achieves performance of upward of 25 Gflops. Finally, two system-design EDA vendors-Alternative System Concepts and CoWare-claim the best way to get a handle on low-power design is to consider power issues at the beginning of the design process.