Designing for low power can drive you crazy. What is commonly referred to as "low-power design" actually comprises two different, but related, activities. The first is power minimization to prolong battery life; the second is power-integrity management, or overseeing the delivery of power to various parts of the chip, as well as the effects of nonideal power sources on a design's timing and functionality.

Power minimization seeks to reduce power consumption, be it average power, instantaneous power or both. It may be directed at all modes of operation or only a particular power mode, such as standby or sleep mode. It may focus only on dynamic power, only on leakage power or on the total. By comparison, power-integrity management seeks to illuminate and minimize the effects of power on the design. These effects include timing, noise, reliability and cost.

The optimization of these various effects becomes more complex as designers go to greater lengths to control the effects. For example, the reduction of power supply voltages over the last several years, from the long-standing 5-volt standard to around 1 V, exacerbates concerns such as large on-chip supply currents and minuscule noise margins. The use of multiple voltages to obtain higher performance or to interface to devices running at higher voltages creates additional problems.

Here's the good news on power: A number of improved EDA tools are now available. For example, power can be calculated early by utilizing tools that estimate power from a high-level register-transfer-level (RTL) description, while later detailed analyses of dynamic supply currents flowing through on-chip power distribution networks can be obtained via the use of power-rail analyzers. In between, power can be calculated and optimized at the gate level, after synthesis and before physical design.

The most effective employment in these applications is dependent on a well-structured design flow. For power optimization as for other parameters such as performance and cost, it is critical to design the system properly at the beginning and successively refine it as the project proceeds. Such a multilevel approach increases the likelihood of meeting design goals by providing both early visibility into critical issues as well as multiple opportunities for mitigation.

Much of digital design today utilizes a top-down or modified top-down design flow. In conventional practice, detailed design information tends to follow a "feedback" flow-information about particular power characteristics does not become available until the design has progressed to the lower abstraction levels. A feedback flow features a relatively lengthy loop from the analysis results obtained at the gate or transistor level back up to the design tasks at RTL and above, so information about the design's power characteristics is not obtained until quite late in the design process. Once this information is available, it is fed back to the higher abstraction levels to be used in determining how to deal with particular power concerns. The further the lower-level power analysis results exceed the target specification, the higher the abstraction level in which the design must be changed.

By comparison, a "feed-forward" approach replaces these lengthy, cross-abstraction feedback loops with more efficient abstraction-specific loops (see figure). Thus the design that is fed forward to the lower abstraction levels is much less likely to be fed back for reworking, and the analysis performed at the lower levels essentially becomes a verification task. The key concept is to identify, as early as possible, the design parameters and trade-offs that are required to meet the project's power specs. This helps to ensure that the design being fed forward is fundamentally capable of achieving the power targets. Later in the design flow, optimizations at the lower levels can be used to further minimize the power as desired.

The feed-forward flow is enabled by a high-level analysis tool that can accurately predict power characteristics. These early, high-level analysis capabilities are used to make informed trade-offs like which algorithms and architectures to employ without having to resort to detailed design efforts or low-level implementations in order to assess performance against the target power specification. Compared with the traditional top-down methods, the early-prediction technology adds a key advantage.

In parallel with, or sometimes ahead of, the architecture development is the design of the library macro functions and custom elements like data path cells. These are used in the subsequent implementation phase in which the RTL design is converted into a gate-level netlist.

At this point, whatever is appropriate is optimized again and power is re-estimated with more detailed information such as floor-planned wiring capacitances. The power grid is planned and laid out using this power data.

Once the design has been synthesized into a technology-mapped, gate-level netlist, lower-level power can be optimized with a tool to further reduce dynamic or leakage power consumption or both. The particular optimizations employed will be determined by specific goals or problems such as battery life or noise margin repair.

These optimizations can be performed either before (using estimated wiring parasitics) or after routing (using extracted wiring parasitics). In either case, after the design has been routed and optimized, a final tapeout verification and electrical verification check is performed with an electrical sign-off tool. In this step, power is calculated and used to compute and validate key design parameters such as total power consumption in active and standby modes, junction temperatures, power-supply droop, noise margins and signal delays.

Thus, power is analyzed and optimized multiple times at each abstraction layer following the feed-forward approach. Each analysis is successively refined from the previous one by using information fed forward from prior design decisions along with new details produced by the most recent design activities. Each optimization, at the various abstraction layers, results in more efficient logic structures to feed forward to the downstream design tasks, thereby successively squeezing out the wasted power. This approach encourages design efforts to be spent up front, at the higher abstraction levels, where design efforts are most effective in terms of minimizing and controlling power.

Jerry Frenkil is vice president, advanced development, at Sequence Design Inc. (Santa Clara, Calif.).

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