Most power-reduction techniques are implemented at the register-transfer level (RTL) or gate level. Clock gating that "shuts off' unnecessary power consumption in an ASIC is by far the most popular power-reduction technique. Other techniques include using sleep modes, better logic design and efficient resource optimization. Commercial tools automate some techniques such as clock gating and logic design at the RTL level. However, power savings due to RTL techniques tend to max out at a power reduction of about one-third compared to performance-optimized design. Any further improvement requires significant manual effort and redesigning that is often based on experience. Needless to say, manual techniques tend to be time consuming and further prolong already long design cycles.

By moving up the abstraction ladder to the system level, significant opportunities can open up for power optimization. By employing techniques such as scheduling and optimization, while keeping track of switching activity in the design, designers can explore a significantly larger design space and offer the best possible solution under the given constraints. The synthesis tool offered by Alternative System Concepts (ASC) works at the system level and uses several advanced techniques to optimize power in a design.

The accompanying table shows the difference in power savings when using the RTL and system-level design abstraction. A system-level power-synthesis tool reads in high-level (system level) algorithmic descriptions and generates power-optimized RTL architectures. During synthesis, the tool chooses different functional blocks in a circuit that consumes minimum power. A pre-characterized RTL component library is used to estimate power in the circuit. It takes switching and leakage power into account during scheduling and binding processes and generates the architecture with minimum static and dynamic power, while satisfying user-specified constraints.

The architecture is further constructed in such a way that, when a functional unit is going to be idle in the next control step, the registers from which it takes its inputs do not load in a new value. Such a circuit eliminates spurious activity in the design by allocating extra registers. By doing that, the need for extensive clock gating is reduced, thereby simplifying downstream design flow. Since at the system level, the tool knows exact number of registers allocated and corresponding area trade-off, it arrives at a far better solution to reduce the power while creating minimum area overhead.

Initial results have shown that the power savings offered by high-level optimization are of the order of 2x to 20x at the same performance level, compared to area-optimized designs. Since at the system level there is much larger space to explore, results can be dramatically better than the RTL-optimized results. System-level optimization techniques also consider input-vector stimulus from a different module (such as test bench) and thus the design is optimized for switching activity corresponding to the data set of interest to designer.

There are several reasons why designers should consider adopting system-level methodologies for power optimization: