United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 


Testable SoCs
Print this article Email this article Reprints RSS Digital Edition

EE Times



Designers confront speed, complexity issues
For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability rests squarely on the shoulders of the design team. If it's postponed until late in the design flow, even, the odds of problems skyrocket.


  • How systems level considerations impact cost-effective Gigabit Ethernet PHYs
  • Test flow speeds up MP3 decoder development to eight weeks


  • Testing the HyperTransport PHY core
  • Every new design is an ESD test chip
  • Design for testability: separating the myths from reality






  •   Free Subscription to EE Times
    First Name Last Name
    Company Name Title
    Email address
      Click here for your Free Subscription to EETimes Europe
     
    CAREER CENTER
    Looking for a new job?
    SEARCH JOBS
    SPONSOR

    RECENT JOB POSTINGS
    CAREER NEWS
    SRC Expands R&D Centers
    The Semiconductor Research Corp has added a new center to its university R&D efforts.

    For more great jobs, career related news, features and services, please visit EETimes' Career Center.


    All White Papers »   

     
    Education and
    Learning


    Learn Now:












    Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
    Network Websites
    International
    Network Features




    All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
    Privacy Statement | Terms of Service | About