This is an exciting time for anyone involved in silicon-on-insulator technology, as leading companies move from partially depleted SOI to strained silicon channels on SOI substrates. While IBM and Motorola for more than a year have used SOI to make PowerPC processors — Motorola has made about 750,000 G4 processors on SOI to date -SOI moves into higher volumes late this year as AMD begins making its Hammer 64-bit processor on SOI substrates.

This week's In Focus offers a full view on the how and whys of SOI technology — from the industry need for ongoing process developments and device production to application realities along with some analysis of SOI's critics.

In his contribution to the section, Carlos Mazure, chief technology officer of SOI wafer manufacturer Soitec (Grenoble, France), explains how silicon on a fused quartz substrate (SOQ) and silicon on glass will enable ICs to be developed on transparent substrates. And, Jean-Luc Pelloie, chairman of Soisic, also Grenoble-based, describes how one can gain the speed advantages of SOI while learning to handle the increase in complexity at the circuit design level.

Meanwhile, IBM fellow Ghavam G. Shahidi, who pioneered the company's SOI effort, explains how IBM is moving beyond simple SOI structures to SOI with strained silicon, known as SGOI for strained Si on SiGe on oxide. SGOI, Shahidi argues, results in a higher strain level and higher current in silicon at a given defect density.

The challenges of controlling the diffusion of dopants used to form source and drain extensions are detailed in a contribution by a team of Applied Materials and Soitec researchers. They have designed a buried oxide (BOX) interface that provides a sharp junction which is shallower and more abrupt than junctions obtained with bulk Si substrates. The author's conclusion: the use of SOI substrates can enable the extension of today's ion implant and anneal technologies to the 65-nm node and possibly beyond.

And, in our exclusive online coverage, AMD senior vice president, Bill Siegle explains how SOI reduces transistor capacitance by 20 to 25 percent, keeping the Hammer MPU power budget within 70 Watts while taking the transistor count up to 100 million transistors.

Many on the research end expect SOI to branch out to new fields beyond high-performance processors. Motorola managers, Michael Mendicino and Craig S. Lage, look into their crystal ball, arguing that if SOI wafer costs continue to come down, SOI will branch out into networking and communications applications. Using SOI in SoC devices will require memory, and Motorola finds promise in the capacitorless 1T DRAM recently announced by the Swiss Federal Institute of Technology.

Soitec CEO, Andre Auberton-Herve, provides an outline of the metrology and manufacturing challenges facing the silicon industry as SOI substrates move to 300-mm diameters and stringent uniformity levels. And, researchers from another French company, Tronic's Microsystems, offer their perspective on using SOI in MEMS devices such as pressure sensing elements small enough for medical implants, and optical switches which feature low insertion loss. SOI substrates allow sacrificial oxide layers to be stripped away to create MEMS gyroscopes, resonant strain gauges, and seismic detectors, in which a high resonant Q factor is the key parameter.