This week's In Focus offers a cross-section of such approaches from hard- and soft-IP vendors, major semiconductor companies and EDA tool houses. Depending on the tools or services a company can bring to the process and the type of application being tackled, IP reuse can take very different forms.

For example, engineers at Mentor Graphics Corp. propose the platform- based approach, where a large part of the design is a standard, complex core, such as a microprocessor or DSP, to which specialized IP blocks add a variety of individual functionality. But in order to add unique circuit elements to standard cores, designers must use standards-compliant IP or the project can get out of control. As Michael Kaskowitz, general manager of Mentor Graphics' Intellectual Property Division (San Jose, Calif.), explains in his article, "Preverified, compliant standards-based IP establishes functionally correct operation, shortening the time-to-working silicon. This is the whole point of IP, after all. If it's not easy to implement, what's the point? If it's not easy to use and deploy, it doesn't help you meet your schedule."

Not only must specific design flows change, a company might have to review its entire business model due to the wide number of issues involved in reusing IP. Ray Abrishami, senior director at Fujitsu Microelectronics America Inc. (San Jose), looks at the big picture, observing that "there are also other key ingredients that we must understand and appreciate in order to make this technology evolution cost-effective and successful. Among them: the need for knowledge disclosure and transfer, along with logistical, technical and legal provisions."

Meanwhile, other contributors take up specific issues — how to tackle specialized applications, whether to use hard or soft IP, and the specialized demands of specific circuit types such as memory or analog and mixed-signal designs.

One interesting new approach is a synthesizable interconnect system, which relieves the designer of many low-level timing and power issues. Described in an exclusive online article by Howard Sachs, president and chief executive officer of Telairity Semiconductor Inc. (Santa Clara, Calif.), the lower metal layers are designed to work with precharacterized small-scale hard-IP blocks so that a wide variety of basic functions can be easily merged to create designs that rival custom circuits in terms of speed and power dissipation.