SoC interconnect crisis: Path delays cancel speed increase
An integrated circuit at 0.25-micron design rules contains about 800 meters of wire interconnect, draining 50 percent of the power consumed by the circuit. When 0.01-micron chips emerge, they will typically have a total of 5 km of wire interconnect, all of it embedded in a piece of silicon only 2 cm on a side.
Metal layers a key to interconnect delay?
Signal integrity a challenge in IC design
COT design path eyes interconnect crunch
Needed: High-level interconnect methodology for nanometer ICs
Custom SoC designers must consider interconnect effects
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