The whole idea of reusable intellectual property (IP) is that the original designer does the work and you don't have to repeat it. If that's true for the design part of IP creation, it certainly should hold for the 70 percent of total engineering effort that goes into verification. After all, they wouldn't license it to you if it didn't work, right?

But anecdotal evidence suggests that most experienced design teams will spend at least as much time on verification of existing IP as they will on newly created blocks. Just where this effort all goes depends on the nature of the intellectual property, the application and the nature of the vendor's relationship with the design team.

Surprisingly, a good deal of effort goes into verifying the internal function of the IP block. Even though this is exactly where IP developers will spend most of their time, many design managers report that they would not consider using a block of IP-even hard IP-until it has met the same verification coverage criteria as their own work. Some will take this even further, particularly for analog IP, refusing to license a block that doesn't already exist in silicon.

That leaves the rest of the job: verifying that the design team's particular instance of the IP is correct and that it behaves as required with the other blocks on the chip. In the case of I/O blocks, this can take on a whole new meaning, as high-speed I/Os may need to be sized and timed for the particular package and board environment in which they will be used.

Our articles this week survey this whole terrain. 0-In's Tom Anderson leads off with a practical checklist for verifying digital IP. Palmchip firmware engineer Linda Yang adds another view: that the system firmware may be a vital tool in verification. And TriCN VP John Ellis adds a study on the verification of delicate I/O blocks. From a different viewpoint, Agilent program manager Jay McDougal looks specifically at internal verification of CPUs. And on the Web, IP and tool vendors Altrabit Networks, ARC, LSI Logic, Synopsys, Tensilica and Denali add their views of the verification process.

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