Using embedded silicon intellectual property (IP) from multiple sources has become common in system-on-chip (SoC) designs. But the time and effort required to integrate and verify these components at the level of the completed system places a burden on both hardware designers and embedded software developers. Software developers need accurate models of the SoC's peripherals and interfaces, as well as of the processor, for testing and debugging application firmware before the design is taped out. This situation is even more critical in SoC platforms based on configurable processors and peripheral IP.

Developers working with configurable SoCs need a robust co-simulation and hardware/software co-verification environment, and a configurable testbench methodology, that can simulate the SoC design in its final form. Such a methodology/environment lets developers concurrently run a typical application on the processor while data is sent to and received from the peripherals, while the environment simultaneously performs error checking and test coverage analyses and analyzes system performance under such real-world stresses.

Unfortunately, most IP suppliers do not provide either a flexible, extensible system-level functional verification environment or co-verification of hardware and software in a single, well-integrated environment. Ideally, such an environment should minimize simulation effort and runtime, maximize the ability to run complex system interactions and execute real software, and ensure high test coverage.

Instead, most vendors' IP verification strategies involve extensively testing each block separately with a test configuration different from those used for the other IP blocks. System testing is limited to basic interaction between blocks in the base system: processor IP, memory IP, a set of peripheral IP, and a common system bus. Most tests are fixed, with checking statistically embedded in the test code, and focus only on certain aspects of the system. Nor can users easily try out the different configurations made possible by configurable processor and peripheral IP, test complex interactions between blocks, analyze hardware and software performance, or develop and test application code using the same simulation platform.

Traditional system-level verification (SLV) solutions are testbenches coded in an HDL, such as Verilog. Yet these are non-portable, forcing users to re-create testbenches and tests to verify IP in the final system, as well as inflexible, requiring many tedious changes whenever the system is modified. In addition, real-time checking and re-use of verification code is difficult. These HDL-based environments are also inadequate for firmware developers, who need embedded software tools, fast processor execution models, and a software approach for controlling test flow and testbench utilities.

A better SLV environment should include an integrated hardware/software simulation and debugging environment, which can be hooked up via actual interfaces to a testbench that controls the SoC and everything else contained in the final testing environment. To properly test configurable IP, the testbench and its models must be configurable to adapt to customers' application requirements. For example, it could test a processor sending packets of data down an Ethernet interface at 10/100 megabits/second to an outside system and back, while simultaneously testing an application, which requires running the RTOS and protocol stack. This could be accomplished if the development environment included a testbench utility to perform hardware checking and diagnostics, since the libraries and test code would become very simple, and could be embedded in the application.

What's needed is a methodology for system-level functional verification of hardware IP that also forms a platform for simulating software IP. It allows the inclusion of random-generated system events or error injections, run concurrently with test code for processor and peripherals to mimic real-life stimuli; self-checking, automatically-generated tests that use reference models and scoreboard techniques, eliminating the need to embed such functionality in the test code; and SLV events for specific IP--whether that IP originates with the user or with the IP provider--that can be reused for the entire SoC.

ARC International performs extensive SLV configurations and testing, in order to verify that a system containing IP from ARC functions correctly and meets the demands of customers' systems, thus saving development time. The SLV environment which ARC uses integrates both a processor verification environment and a dataflow verification environment in order to concurrently verify at the system level the ARC extendable processor core, the peripherals for data flow, and selectable ARC system configurations. The environment includes a testbench, based on Synopsys' Vera testbench language; the device under test, consisting of a base system configuration; and ARC's MetaWare tool chain, which contains the option of replacing the processor's RTL code with the Instruction Set Simulator (ISS). It is configurable and adaptable to the different types of systems that can be created using ARC tools. It has been architected to perform hardware and software checking at the system level, in which packets of data are injected into the system, complex instruction sequences are executed, and system interactions are checked. Functional tests include confidence tests selectable for the particular configuration.

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