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SOI and beyond
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CMOS scaling requires materials advances
The challenges facing CMOS scaling increase with each technology node, presenting materials scientists, metrologists and process technologists with plenty of good work to do.


  • Crafting wafer-scale strained silicon
  • Engineered substrates boost performance
  • Inside composite substrates
  • Silicon germanium challenges metrology
  • High-k strides reopen door to germanium


  • SOI and strained silicon complement each other
  • Non-Classical CMOS: the "Ultimate" MOSFET Device






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