Chalcogenide RAM, made of the Ge2Sb2Te5 materials, has recently been regarded as the most promising next-generation memory. (Ge is germanium, Sb is antimony and Te is tellurium.) With a name derived from chalcogens, which are compounds of inorganic chemistry, chalcogenides contain oxygen, sulfur, selenium, tellurium and polonium. Chalcogenide RAM is nonvolatile, boasts access speed comparable to that of DRAM and possesses advantages in scalability, high sensing margin, low energy consumption and endurance to cycling. The structure and processing of chalcogenide memory are much simpler than in other next-generation memories such as MRAM and ferroelectric RAM. In a chalcogenide memory cell, the data is stored in a flat chalcogenide layer that can be deposited near the end of the CMOS interconnect process. Therefore, disturbance of the CMOS process is minimal, making it ideal for systems-on-chip.

A chalcogenide memory is achieved by using the reversible high/low resistance of two structural phases. Chalcogenide in the amorphous phase (reset state) shows high resistance; the crystalline phase shows low resistance. The ratio between them can be greater than 1,000 times, which provides high sensing margins. In the reset state, the resistance at the low electric field is high because there are only a few carriers in the material.

Once the applied bias is larger than the threshold voltage, threshold switching occurs and the material turns into a dynamic on state. In this state, the carrier concentration is high and the resistance is as low as that in the crystalline state.

To drive sufficient energy into the device, the state is changed from reset to set in the dynamic on state for a device in the reset state. For a chalcogenide device, temperature and the time above the crystallization temperature (Tx) are the key factors for programming.

To program a cell from set to reset, sufficient energy must be driven into the chalcogenide device and the local temperature must be raised to above the melting temperature (Tm). Only a short time should be spent above Tm to avoid heating the surrounding materials. Rapid quenching is required after the local heating to achieve an amorphous phase (reset). Taking Ge2Sb2Te5 as an example, the time between Tm and Tx should be less than 50 nanoseconds.

On the other hand, to program a cell from reset to set, the local temperature is raised higher than Tx longer than 50 ns (for Ge2Sb2Te5) to allow crystallization to complete. To read a chalcogenide memory device, a "read" voltage is applied on the device; thus we can sense the current difference resulting from the different device resistance. The read voltage must be lower than the threshold voltage to avoid changing the material state.

Currently, chalcogenides are used in reversible optical information storage such as CD-RW and DVD-RW. Compounds such as Ge2Sb2Te5 can change phase from amorphous to crystalline in 50 ns after proper laser exposure. However, the crystallization speed of a germanium-antimony-tellurium material tends to decrease with thinner films. To avoid this, it is suggested tin be doped into a Ge-Sb-Te compound to form a Ge-Sb-Sn-Te compound and increase the crystallization speed.

Ultrathin chalcogenide film can decrease the heating region and the current required. Moreover, the device resistance is a function of the chalcogenide film thickness: The thinner the film, the lower the resistance and, thus, the lower the programming voltage. However, high programming speed is critical not only for system performance, but more importantly, to reduce power consumption. Therefore, we have investigated the programming (set/reset) speed of ultrathin chalcogenide films. In this work, chalcogenide devices are fabricated with 180-nanometer-node CMOS technology. The properties of ultrathin undoped and Sn-doped Ge2Sb2Te5 are compared and the electrical properties of the devices are reported.

Standard 180-nm processes are used to establish the selection circuit and the chalcogenide device. The tungsten bottom electrode has a diameter of 220 nm; the chalcogenide film (approximately 55 nm thick) and the top electrode TiW (approximately 110 nm thick) are deposited by dc sputtering.

A chalcogenide device consists of a top electrode, a chalcogenide layer and a bottom electrode. The materials are TiW, undoped or Sn-doped Ge2Sb2Te5 and tungsten, respectively. An Agilent-4156A parameter analyzer and an Agilent-81110 dual-channel pulse generator are used to measure the I-V characteristics and drive in the set/reset pulses, respectively. Transmission electronic microscopy is used to investigate the microstructure and the phase of the chalcogenide device. The film phase is investigated by X-ray diffraction. A typical architecture of the chalcogenide RAM has the memory cell made of a chalcogenide device (serving as the memory element) and a transistor device (serving as the steering element).

The set and reset properties of chalcogenide memory devices were investigated. When the pulse voltage is 1 V, the resistance remains high because insufficient energy is driven into the device. For pulse voltage V = 1.5 V and V = 2 V, the resistance is decreased after set pulse and the resistance declines as pulse width increases. Stable low resistance (about 50 kohms) is obtained when the pulse widths are longer than 200 ns and 400 ns for V = 1.5 V and V = 2 V, respectively. Thus the set process for these ultrathin films is much slower than the 50 ns reported for thicker films. The set resistance of tin-doped Ge2Sb2Te5 decreased after set pulses of 40 ns.

The reset testing results of undoped Ge2Sb2Te5 show that for short reset pulses (less than 40 ns), the resistance increases with pulse voltage. This indicates that when the pulse width is short, increasing the pulse voltage drives more energy into the device and melts more parts of the chalcogenide layer; therefore device resistance increases with pulse width and voltage. When the voltage is high and the pulse width is too long (for example, 5 V, 80 ns), some part of the chalcogenide begins to crystallize and decreases the resistance slightly.

Comparing tin-doped and undoped Ge2Sb2Te5 memories, the programming speed-in the case of set and reset-of the doped Ge2Sb2Te5 is faster than with undoped Ge2Sb2Te5. The reading speed is also faster for the doped version because the resistance of the chalcogenide is decreased to 4 kohms from 50 kohms.

Y.C. Chen, C.T. Chen, J.Y. Yu, C.Y. Lee, C.F. Chen, S.L. Lung and Rich Liu work for Macronix International Co. Ltd. (Hsinchu, Taiwan).