In this week's In Focus section, we'll do some weed whacking with a handful of contributions that look at different challenges of ultradeep-submicron design and suggest ways to push on through.

A few bonus papers in the mix come to you courtesy of contributors to the International Solid-State Circuits Conference, which opens this week in San Francisco. The first is from the European R&D consortium Mesa+ and is related to deep-submicron design, but the other is the condensed keynote speech of Nokia Mobile Phones CTO Yrjo Neuvo. It's a little off topic-focusing on the growing complexity and demands of cellular systems-but it's nonetheless interesting so we wanted to give you a sneak peek.

Few doubt the awesome challenges facing the industry as it marches doggedly down through the generations of process technology. They are varied and far-ranging, just like our submissions.

The folks at AMI Semiconductor Inc. confront the difficulty by advising engineers to avoid it for a little while longer. In other words, consider the more relaxed rules of a structured ASIC, which trades some performance for higher yield, reliability and faster time-to-market.

Another industrywide fly in the ointment has undoubtedly been integration of low-k materials into the dielectric stack. Michael Gostein, chief technologist at Philips Advanced Metrology Systems, focuses on better testing of low-k materials, through surface-wave metrology, to decrease the likelihood of low-k materials fouling up the chip.

A good complement to this piece is the online contribution on packaging from Texas Instruments Inc. engineers Greg Hotchkiss and Vish Sundararaman. They explore the stress impact of today's packaging techniques on low-k silicon and highlight a few solutions the packaging industry is working on, such as cutting dice with lasers instead of saws.