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SOC: IP VERIFICATION
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EE Times



IP TripTik needed on system-on-chip highway
By this fall, hundreds of system-on-chip design teams around the world will be targeting 90-nanometer process technologies. Though schedules vary, the leading foundries and integrated device manufacturers expect to make system-chips on 90-nm design rules by next spring.


  • Standards eye functional verification
  • Method backs block-to-SoC verification


  • Verifying timing of external IP key to SoC success
  • Integrating IP with assertion- based verification
  • RTL prototyping: a hardware/software co-verification solution
  • SoC/IP designs need next-gen solutions for integration verification
  • Plugging the verification time sink
  • HDL advances bolster complete system verification
  • Building systems at the silicon level: time, cost, design constraints
  • What are the main challenges to successful IP integration?






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