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Choosing the Right Interconnect, Part 1
Next-generation computer servers and communications systems need to support data rates of multiple Gbits/second and silicon running at frequencies beyond a gigahertz. In this Giga era, engineers face strategic choices around which chip-to-chip and backplane interconnects they will use. They must also determine whether they will make or buy the key intellectual property they need, and how they will integrate the key pieces of the puzzle into a final system design.
EE Times has launched a two-part focus on interconnect design to better understand these issues. The first part of this project features:
- A report on a focus group with a sampling of systems engineers
- A report based on interviews by Editor at large Rick Merritt with a cross-section of engineers working in the field
- Analyst perspective on the industry issues surrounding interconnect
Stay tuned for the second part of our project in April. It will include an in-depth Web survey of systems engineers and a NetSeminar summarizing the findings of our work.
 Click for panel discussion audio (15MB)
Welcome to the Giga Era
Next-generation communications and computer systems now being designed will typically handle data rates of multiple gigabits/second.
High-speed I/O stars rise for gigabit designs
Todd Westerhoff is an example of the new breed of engineers rising to meet the Giga Era.
Need for simulation models is not being met
Many chip and connector vendors are failing to deliver the detailed component simulation models that enable engineers to design in those parts in an accurate and timely way.
'Agnostic' engineers see shift to PCI Express
Engineers want to remain agnostic. Whatever high-speed interconnect works best for a given design is what they will use, they say.
EEs bid adieu to parallel PCI
One of the big shifts in interconnect has been toward fast serial interconnects and away from parallel buses like the omnipresent Peripheral Component Interconnect. In its latest incarnation, PCI-X has been pushed to 266 and 533 MHz, but that appears to be the end of its road map.
Understanding backplane, chip-to-chip tech
High-speed interconnects may be used to link chips, boards or systems. The distance between target devices is the major difference.
Express, serial ATA gain but comms is unclear
The shift from parallel PCI to PCI Express is happening quickly, as is the shift from the parallel IDE to the serial-ATA hard-disk interface. But it's not yet clear how the Advanced Switching, RapidIO and HyperTransport rivalry will play out among communications OEMs.
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