A gigabit per year. That's the speed at which designers are accelerating, our recent Web survey of 243 backplane and chip-to-chip interconnect developers found. In this special section,"Choosing the right interconnect," Part 2, we report on where computer, communications and storage networking designers say they are now and where they expect to go. The designers tell us what they consider their biggest design challenges and offer assessments on a host of related technologies. In addition, we provide views of the road ahead in interconnect design.

Consultant Lee Ritchey discusses the simulation models and documentation that silicon vendors must provide if they are to enable a smooth transition to the next generation of high-speed serial interconnects. He also details the problems engineers encounter with the sometimes-substandard models and data sheets available today.

What's more, R&D engineers at Lucent Technologies and NEC look beyond today's 10 Gbits/second. In separate papers, they say why the industry will need to move to duobinary signaling if it is to reach 12-, 20- and even 40-Gbit signaling rates over copper. We hope this final installation in our Industry challenges series on interconnect design helps you navigate the giga era.

Net Seminar Thursday, April 21 2005 11:00am PT / 2:00pm ET EE Times editor-at-large Rick Merritt leads a NetSeminar panel discussion, disclosing results of a recent survey of OEM engineers on which chip-to-chip and backplane interconnects they are using today, and expect to be using tomorrow, and why they are choosing them. This is especially enlightening at a time when a variety of different options are becoming available--including Advanced Switching, Backplane Ethernet, Hypertransport, Infiniband, PCI Express and RapidIO. The panel will also report on trends the survey uncovered in the use and integration of high-speed serdes, signal conditioning methods and simulation models. Panelists will provide their assessments of what are the critical interconnect issues going forward and how vendors can better address them. Register today for this exclusive NetSeminar and pose your questions.

Choosing the right interconnect
A gigabit per year. That's the speed at which designers are accelerating, our recent Web survey of 243 backplane and chip-to-chip interconnect developers found.

Methodology
Our Web survey was conducted by e-mail solicitation between Feb. 9 and Feb. 25. A total of 243 people, primarily in North America, responded to the survey, giving us a confidence interval of 6 percent.

Designers chart progress in the gigabit era
Systems designers have stepped into the era of gigabit-class interconnects in a significant way, and many are poised to ratchet up the speeds of their systems significantly in the next two years. But plenty of pitfalls line the path for next-generation backplane and chip-to-chip links on this journey.

E'net, Express ride into mainstream
We are heading into an Ethernet and Express world. An analysis of the 243 responses to our Web survey indicates there is still some significant experimentation amid diverse new and old interconnect technologies, but these are largely second-tier options today and probably still will be tomorrow.

Inside chip makers' modeling problem
The march of technology has made it important for all digital designers and component suppliers to use the same skills that were once only required of such supercomputer engineers as Cray and IBM and their suppliers.

Electrical duobinary signaling for backplane transmission at 25 Gbits/s and beyond
For at least a decade the question on the table has been whether electrical interconnect speeds could keep pace with the ever-increasing capacity and bandwidth of telecommunication switches, routers and servers.

12-Gbit/s duobinary signaling with x2 oversampled edge equalization
In recent chip-to-chip and backplane data transfers on printed-circuit boards, data rates are limited not by the operating speeds of the circuits in the transceivers but by the bandwidth of the transmission media.

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