A gigabit per year. That's the speed at which designers are accelerating, our recent Web survey of 243 backplane and chip-to-chip interconnect developers found.
In this special section, we report on where computer, communications and storage networking designers say they are now and where they expect to go. The designers tell us what they consider their biggest design challenges and offer opinions on a host of related technologies. In addition, print and online contributors provide views of the road ahead in interconnect design.
Consultant Lee Ritchey discusses the simulation models and documentation that silicon vendors must provide if they are to enable a smooth transition to the next generation of high-speed serial interconnects. He also details the problems engineers encounter with the sometimes-substandard models and data sheets available today.
Online, R&D engineers at Lucent Technologies and NEC look beyond today's 10 Gbits/second. In separate papers, they say why the industry will need to move to duobinary signaling if it is to reach 12-, 20- and even 40-Gbit signaling rates over copper (www.eetimes.com/industrychallenges/).
We hope this final installation in our Industry challenges series on interconnect design helps you navigate the giga era.