Systems designers have stepped into the era of gigabit-class interconnects in a significant way, and many are poised to ratchet up the speeds of their systems significantly in the next two years. But plenty of pitfalls line the path for next-generation backplane and chip-to-chip links on this journey. Chief among them are maintaining signal integrity, simulating product behavior and choosing the right standards.
We asked 243 engineers working on these interconnects in a variety of communications, computer and storage systems markets to tell us where they are, where they are going and what their issues are. In this special section, we share the details of that Web survey.
To be precise, respondents told us on average that their current systems run at rates of up to 3.02 Gbits/second, and half of them have crossed the 3-Gbit threshold. As a group, they expect that within two years, their top designs will be running at an average of 6.15 Gbits/s.
A subset of pioneers (18 percent) has already designed systems with interconnects that hit 10 Gbits. Others suggest they will join that group within two years, leapfrogging a 6-Gbit generation to go directly to 10 Gbits.
Engineers are maintaining this Gbit/year pace at the same time that they are tackling two other transitions. More than three-quarters (77.3 percent) of respondents said they are very or somewhat likely to shift from parallel to serial links over the next two years. A smaller, though still significant, majority of respondents (68.4 percent) said they expect to increase their use of backplanes in their system designs.
A closer look at the numbers shows that today's designs are spread fairly evenly across a wide range of data rates, from 1 to 10 Gbits. A slightly larger fraction is at less than 2 Gbits. The smallest group is in a sort of no man's land, between 7 and 10 Gbits. Designs will cluster more at the extremes of the range in two years, when as many as 35.4 percent of designers said they will be at 10 Gbits. The second-largest group (18.9 percent) said they will still be under 2 Gbits.
The rapid doubling of the 10-Gbit group suggests that some designers will leapfrog 5- to 6-Gbit designs. Indeed, the median data rate in two years for respondents from small companies (with revenue less than $50 million) is a whopping 9.1 Gbits/s, suggesting that many aggressive startups and design houses plan to use the Gbit transition to gain a market advantage.
As a corollary, the 7- to 10-Gbit range, which is the smallest slice of the market today, will occupy the same position in two years, according to our survey. Vendors would be advised to take heed of that finding.
On the serial path
Most designers are taking a serial route to Gbit speeds. The majority of respondents (64 percent) said they use serializer/deserializer (serdes) devices. Interestingly, large companies (those with more than $1 billion in revenue) push this trend slightly harder (at 69.8 percent) than the usually risk-taking small companies. This may indicate that the shift to serial interconnects requires new and deeper skill sets, which the large companies are more apt to have in-house.
On average, respondents currently use serdes running at 3.74 Gbits/s and plan to use serdes running at 6.14 in two years. This finding validates the overall interconnect speeds respondents listed on the survey, and again the spread of actual speeds is fairly broad.
Most respondents are at or below the Xaui 3.125 Gbit rate and plan a move to the doubled version, at 6.25 Gbits. While the Xaui rate is the single largest category of serdes used today (35.5 percent), the 10-Gbit rate will become the largest single category in two years (28.2 percent). Our survey indicates that the 10-Gbit serdes users will more than triple in size over the next two years, which again suggests that some people are skipping a 5- to 6-Gbit generation and going directly to 10 Gbits.
A closer analysis shows small companies are driving this move to leapfrog to 10-Gbit serdes. Only 7.7 percent of small companies plan to use what will be the mainstream 6.25-Gbit serdes in two years, but 43.6 percent plan to use 10-Gbit parts.
By contrast, large companies will primarily use 6.25-Gbit serdes (29.3 percent), confirming that this will become a mainstream segment. Large companies also stand out in their use of 12-Gbit serdes (6.9 percent), indicating they will try to show some in-house technology leadership at this new high ground.
Designers get their serdes from a variety of tried-and-true sources. Large companies tend to rely on in-house development (40 percent) and ASICs (37 percent) as their sources of serdes, while medium-sized companies (between $1 billion and $50 million in revenue) mainly tap merchant chip sets (45 percent). Small companies mostly tend to use FPGAs (43.6 percent).
Risk management is the top factor developers consider in choosing a serdes supplier (80.7 percent), followed by time-to-market (71.3 percent) and cost (62 percent). Most companies are using quad serdes (37.8 percent), though a significant number use single- or dual-channel devices. And most are made in 130-nanometer process technology (44.5 percent), although many (30.1 percent) — especially for large companies — are made in 90-nm technology.
The challenges
As a reality check, we asked respondents to fill in a blank box, telling us what their biggest design challenges are with high-speed serial interconnects. We received 164 responses that covered a broad waterfront of issues, including nagging problems with bit error rates, long design cycles for serdes and just finding good high-performance, low-cost connectors.
Nine respondents listed power and heat issues as their main bugaboos in the giga era. Seventeen cited costs, with many noting difficulties with connectors. One said finding a "cost-effective pc board fab for [speeds] greater than 5 Gbits/s" was his most nettlesome problem.
Sixteen respondents said issues with standards and interoperability are their top concerns. In a separate question, 78.5 percent of respondents said they carefully analyze ad hoc industry standards consortia before choosing a technology.
One respondent said his main issue is "picking a standard that can be used and is supported across many [chip] platforms." Another complained that the "10-Gbit/s space [is] currently dominated by proprietary solutions" and that the "choices are limited and expensive."
We also asked respondents for their opinions on 19 interconnect technologies, knowing that designers have been grappling with issues in this area. We learned that Ethernet and PCI Express are set to become the big winners in this space, although significant experimentation is still going on with a host of second-tier options
But the largest group of respondents (45) said their single biggest issue is in maintaining signal integrity in high-speed interconnect design. The second-largest group (24) mentioned the related topic of simulating, verifying or testing high-speed designs.
"The greatest problem that we have is signal trace layout on boards. If impedance is mismatched, or the components are not laid out properly, the high-speed I/O lines get bogged down with digital reflections," said one designer.
"In our product line, the serial interconnects cross many assemblies, and an error in the design has the potential to require redesign of an entire system," said another engineer.
Respondents gave plenty of names to their signal integrity issues, including crosstalk, EMI, jitter, reflections, package noise, skew and static. Scratch the surface of the broad problems in signal integrity, and you find underlying issues in simulation modeling, verification and test.
"The greatest problem that I face is obtaining models that allow accurate simulations of potential solutions prior to implementation," said one respondent.
"The speeds and layout techniques involved make debug almost impossible," said another.
The problem is broad. Accurate modeling, simulation and comprehensive analysis of high-speed serial links include the I/Os, packaging, boards, vias, connectors and cables. "One needs to have accurate models for all of these components and the ability to perform comprehensive solution-space analysis over process, voltage, temperature, PRBS stimulus patterns, etc., to automatically extract waveform quality and eye diagram characteristics," said a designer.
"High-speed serial interconnect verification requires new tools and diagnostics. It is time-consuming to research the technology, and more time-consuming to then research verification methods and tools for the technology," complained another engineer.
In a separate question, only 5 percent of respondents disagreed with the statement that they need better test and measurement tools for high-speed interconnects, and only 8 percent disagreed with the statement that they need better simulation models for serial links. A majority of respondents (68.5 percent) said they often have trouble getting accurate simulation models from their chip vendors.
The SI guys
OEMs appear to be trying to tackle their high-speed-signaling issues by turning to a small group of signal integrity specialists that have significant clout in their organizations. Sixty percent of respondents said their companies employ high-speed serial interconnect specialists. Among large companies, 70 percent said such specialists are on staff.
We selected as pathfinders a group of 86 respondents who said their designs will be at 10 Gbits in two years. These people tended to come either from large or small — not medium-sized — companies across a mix of industry sectors. Eighty-one percent of the pathfinders are using serdes, primarily through ASICs and third-party intellectual-property cores. And 71 percent of the pathfinders employ signal integrity engineers.
The signal integrity specialists have a surprising amount of influence in design decisions, ranking at least fourth in terms of most influential person overall and second and third in some design areas. For instance, SI specialists ranked second to hardware engineers as most influential in qualifying interconnect technology vendors. They ranked third in choosing interconnect technologies. Overall, 73.8 percent of respondents agreed with the statement that signal integrity specialists must approve all systems-level designs before they ship.
When it comes to the question of testing signal integrity, respondents said they prefer to use relatively traditional HSpice (70.1 percent) and Ibis models (51.9 percent). But a significant number said they want less common 3-D models (45.5 percent) to help track effects of chip packages and other issues.
MatLab programs ranked as the first preference (72.5 percent) for predicting bit error rates. MatLab programs also scored relatively highly on overall model preference (at 42.4), presumably because the software is so widely used and familiar. However, 3-D rendering tools scored a close third as a technique for predicting bit error rates (at 25.1 percent), trailing StatEye by a percentage point.
Respondents in our pathfinder group were even stronger in their preference for 3-D models (54.9 percent). Designers working in storage products topped even their score in terms of preference for 3-D models (at 55.6 percent). Likewise, the two groups were stronger than average in their preference for using 3-D rendering tools to predict bit error rates, with the pathfinders at 34.2 percent and the storage OEMs at 36.2 percent.
Finally, as we approach 10-Gbit speeds, many observers have called for a move to new and more-expensive pc board materials as a way to ease signal integrity problems. So we asked whether non-FR4 materials are acceptable in future pc boards.
A majority of respondents (59.8 percent) said the materials are OK, with small companies even more adamant, at 82.6 percent. Embedded-systems designers as a group were also more willing to make the move (72.7 percent), possibly because of a strong contingent of military systems developers for whom performance traditionally is much more significant than cost.
But the fact that a large minority of respondents — and a majority of respondents from medium-sized companies (at 52.2 percent) — are still unwilling to move from today's FR4-based boards suggests that the transition will be a slow one and that this debate will go on for some time to come.
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