In 1980 the rise and fall time of TTL components was in the range of 15 nanoseconds while the ECL used in supercomputers was in the range of half a nanosecond. TTL-based designs were clocked at 10 MHz while ECL computers were clocked at 100 MHz and higher.

Fast forward to 2005. TTL has gone away and ECL has essentially disappeared. Today, CMOS is the technology of choice and it is common for CMOS ICs to have rise times well below half a nanosecond and clock speeds well above a gigahertz. Thus, every engineer and component supplier is now in the supercomputer business.

Despite the fast speed of these CMOS devices, their corresponding package designs and applications notes are still being done using the guidelines that worked for TTL speeds. As a result, many ICs don't work as expected.

Clearly, design engineers depend on IC manufacturers to create products that perform as specified and bet their designs on them, much as the designers of the Golden Gate Bridge depended on the makers of the wire in the cables to make sure the wire was strong enough to do the job. Here is my wish list of the steps I think IC manufacturers should take and the information they should provide systems makers:

Accurately characterize each I/O so OEMs know exactly how it works;

Provide accurate models — Ibis and Spice — so OEMs can properly perform signal integrity analysis;

Design IC packages with sufficient care so that all circuits work properly without interfering with each other;

Provide 3-D models of the IC packages, so OEMs can include them in the signal integrity analysis;

Use the actual parts in real circuits before preparing applications notes; and

Write applications notes based on the part being described and support each design rule with proper engineering analysis.

Unfortunately, chip makers don't always follow all of these steps, and that leads to a host of problems. Throughout 2004 I wrote a monthly column for EE Times that discussed many of the problems design engineers were experiencing as they tried to use very complex, very high-performance ICs in BGA packages. No suppliers were named because the problems have been occurring in a variety of components. But the columns focused on FPGA components because many programs were turning to FPGAs as a rapid way to develop large blocks of logic. I also have a great deal of data from designs that have struggled with these components.

The following problems occur due to poor package design and inadequate application notes:

Two kinds of failure
When packages are not properly designed, two major types of failure occur. First there can be noise on Vdd and ground inside the package resulting from many single-ended outputs switching simultaneously. There can also be coupling of noise from one signal to another inside the package.

Both of those problems are the result of excessively large amounts of parasitic inductance in the power paths of the IC packages. This is a parameter that cannot be controlled by the design engineer. It is in the hands of the IC manufacturer. Designs with these kinds of problems can only be fixed by changing the IC package.

One way to combat shortcomings is to ask an IC supplier for the following during the selection process: a complete list of package parasitics, models of the I/O to use in simulation and examples of real functioning circuits. You should also obtain a set of applications notes with supporting engineering analysis to demonstrate that the design rules are robust.

By Lee W. Ritchey, the president of Speeding Edge, a high-speed signaling consulting company in Glen Ellen, Calif.