At the height of the telecom boom, the crossover from electrical to optical backplane signaling appeared imminent at speeds of 10 to 11 Gbits/second. Now it is clear that copper and silicon technologies have risen to the occasion at this speed. ASICs are available today that enable 11-Gbit/s serial data transmission between two boards across a common backplane.

Achieving these speeds, however, has come at the cost of power and complexity. Based on nonreturn-to-zero (NRZ) signaling, 11-Gbit ASIC devices require substantial signal conditioning to meet the demanding performance requirements for backplane applications. In addition, passive transmission elements like backplane boards and electrical connectors will need to be upgraded to support many 10-Gbit applications.

Within the next decade, signaling rates are projected to hit 25 Gbits/s for a four-lane physical layer for 100-Gbit Ethernet. Beyond that, rates will hit 40 Gbits/s.

Our work in duobinary electrical transmission illuminates how copper and silicon solutions can continue to support the need for speeds of 20 to 30 Gbits/s within the framework of well-known pc-board technology. Duobinary signaling departs from NRZ signaling by using bandwidth compression so that the electrical impairments to transmitting a 20-Gbit/s signal are much as they would be if the signal was running at 10 Gbits/s.

Bandwidth compression techniques are common in wireless and satellite communications. Nonetheless, these techniques were impractical for microwave-speed data transmission because high-bandwidth circuit components were not available, especially in CMOS. Very recently, integrated circuit vendors have developed the microwave-speed low cost silicon logic that enables more-advanced signal processing techniques to be applied to the problem of signal transmission through limited channels.

Four-level pulse amplitude modulation (PAM-4) was one of the first multilevel signaling approaches to show up on the market capable of supporting multigigabit/s data rates. PAM-4 works by transmitting information with a symbol rate that is half the data rate, but each symbol conveys the information normally conveyed in two bits. Specifically, each symbol can have a value of either 0, 1, 2 or 3, representing a pair of data bits, 00, 01, 10 or 11, respectively.

This reduction in bandwidth comes at the cost of requiring a higher signal-to-noise ratio (SNR). Assuming a constant peak-to-peak amplitude at the transmitter regardless of the signaling approach, an additional 9.54 dB of SNR (relative to binary) is needed to obtain the same performance for PAM-4 since we now require four amplitude levels instead of the two levels required for binary. This large SNR penalty prompted us to consider another bandwidth technique.

Duobinary is another multilevel signaling technique that dates back to the 1960s when it was first proposed for band-limited channels.[1] Duobinary requires three signal levels so that each transition is half the amplitude of binary signaling. Again there is an increase in the required SNR of 6 dB relative to binary using the above assumptions; however, this increase is less than that of PAM-4.

The SNR and implementation advantages of duobinary over PAM-4 led us to explore whether current ASIC technology could support a duobinary signaling architecture of more than 25 Gbits/s. Our investigations show that duobinary signaling is capable of transmitting data at 25 to 30 Gbits/s through backplanes and can be implemented in an attractively simple way.

To generate a duobinary signal (see figure 1), binary data is sent through a digital precoder and then through a low-pass filter. The ideal low-pass filter response is that of a delay-and-add filter, with a Z-transform of H(z)=1+z-1, and thus a frequency spectrum of H(f)=1+exp(-j 2 t). This frequency spectrum has a null at half the bit rate, and only the portion below this point is required.

The duobinary data stream has three values: the center value is zero, the top and bottom values both represent a one. The required receiver then takes this three-level data stream and converts it back to binary by effectively full-wave rectifying the data so that the two levels representing a one fold on top of one another.

Of course, for a high-speed data system, a direct-current 25-GHz bandwidth analog full-wave rectifier is not an off-the-shelf component, so digital means are used. In such a system, the data can be converted back to binary using a combination of logic gates and two threshold circuits [2].

What makes duobinary signaling especially advantageous is that the passive transmission lines in backplanes tend to have a frequency response that looks like a low-pass filter. Although the channel rolloff response is not exactly the required shape, it can be augmented, usually with a minimal amount of pre-emphasis so that the combination of equalization and the backplane can act as the required duobinary shaping filter (see figure 2). Thus, the backplane transmission channel essentially becomes part of the transmitter and actually helps us generate the required data filter. This particular approach of using a high-speed backplane as part of the duobinary transmitter for high-speed data transmission has been previously described [2, 3].

The twofold bandwidth compression that duobinary signaling affords has prompted us to examine whether it works for real backplane transmission at twice the speed of 10-Gbit/s NRZ data transmission and higher. While microwave circuit boards can be designed to transmit data at more than 20 Gbits/s, it is by no means obvious that such speeds are practical for the pc board, connectors and distances used for backplanes. For example, material loss goes up at these higher frequencies. Furthermore, connector crosstalk and insertion loss, as well as radiation losses and stub effects can be quite dramatic in the 20+ GHz range.

We recently demonstrated 25-Gbit/s data transmission using a backplane system that was designed for 10-Gbit/s NRZ data transmission [4]. To generate 25-Gbit/s duobinary, we create the required low-pass filter response using a pre-emphasis filter combined with a backplane designed for 10-Gbit/s operation. At the output of the backplane, high-speed logic converts the three-level signal back to 25-Gbit/s NRZ data.

In our demonstration, we used a backplane system with overall trace lengths of 14 to 24 inches consisting of two child boards, two high-performance connectors and a backplane. The total transmission channels had a clean response below 12.5 GHz, the half-frequency point. By a clean response, we mean a response that is not plagued with nulls and erratic spectral behavior, both in amplitude and phase. These effects must be removed from the bandwidth of interest as they impact the transfer function in a complex way, making simple equalization of data signals much more difficult.

Some rolloff, however, is acceptable so we were able to use a medium grade FR4 for the backplane pc board. Nonetheless, since 25-Gbit/s duobinary only requires that most of its energy be below 12.5 GHz, the undesirable high-frequency effects largely have no impact on the performance, whereas they would greatly affect NRZ performance.

Another key application for duobinary that leverages the bandwidth compression is at data rates of 10 Gbits/s and less over legacy boards and backplanes. As pointed out by Charles Byers, a Bell Labs Fellow at Lucent Technologies, "It is highly desirable to preserve backward compatibility with today's boards. There is too much work and product invested in the current scheme to redo the backplane or connectors."

By using duobinary signaling, many of these legacy systems can still meet high-speed demands even though they have passive transmission channels that exhibit undesirable spectral behavior at higher frequencies.

Indium phosphide (InP) technology available today makes it possible to transmit and receive duobinary signals even up to 40 Gbits/s. Microwave transmission lines, if designed correctly, can support transmission at 20 GHz. But the real challenge is in the launch of 40-Gbit/s signals through dense multipin connects through multiple layers of dielectric.

Even for the 20-GHz bandwidth required for duobinary, current connectors and launch structures are severely challenged here. Success at 40 Gbits/s will require improved connect and launch design or migration toward signal processing that provides even more spectral compression. Both are theoretically possible.

Our results indicate that the debate over the crossover from electrical to optical backplanes inside the box should shift to 40 Gbits/s and higher. Both approaches face multiple technology challenges to move from theory to practice. Of course, the ultimate winner will also be decided on key market drivers of cost and implementation.

[1] Lender, The Duobinary Technique for High-Speed Data Transmission, IEEE Transactions on Communications and Electronics, vol. 82, May 1963, pp. 214-218.

[2] Sinsky, Adamiecki, Duelk, 10 Gb/s Electrical Backplane Transmission Using Duobinary Signaling, IMS-2005, Fort Worth, Texas, June 2004.

[3] Sinsky, Duelk, Adamiecki, High-Speed Electrical Backplane Transmission Using Duobinary Signaling, IEEE Trans. On Microwave Theory and Techniques, January 2005.

[4] Adamiecki, Duelk, Sinsky, Mandich, Scalability of Duobinary Signaling for 100 GbE Applications, 25 Gb/s IEEE 802.3ap Task Force Meeting, November, 2004.

By Mary L. Mandich, Ph.D. Technical Manager, Network Hardware Integration Department and Jeffrey H. Sinsky, Ph.D. Member of the Technical Staff, Photonics Networks Research Department Bell Labs Murray Hill, N.J.