Less obvious are the corollaries to this observation. First, the dependence on IP has transmuted most of the work of chip design from RTL creation and synthesis into IP assembly. Second — and most important for our present purposes — this new emphasis on IP assembly to create the majority of the functionality in a chip has made IP selection one of the most critical tasks in the entire chip design.

If that doesn't sound plausible, horror stories abound to confirm it. Whole projects have failed because one significant piece of IP proved unworkable — or, even more frustrating, because several less important pieces refused to be integrated. Schedules have been mangled, and market windows missed. Much more commonly, chips have failed to come even close to their yield targets because of issues with supposedly silicon-proven IP. These are not just annoyances during the design flow. They are threats to the bottom line of a large company or the survival of a small one.

But critical as it is, IP selection has received scant attention from the engineering community. There are few tools to aid the design manager beyond spreadsheets of his or her own contrivance. There are no standards for IP representation, packaging, delivery or evaluation, although these are beginning to emerge in some areas.

Most critically, there is little opportunity for engineers to converse with their most valuable source of information — one another — about how to pick IP.

In an attempt to remedy this situation, EE Times has launched the IP Selection Industry Challenge. This multifaceted program will gather essays and viewpoints from industry experts who are working on the problem. Three such essays, provided by key members of the Virtual Socket Interface Alliance, appear in this special section.

But expert views are just a place to start. Using a combination of focus groups and a global Web questionnaire, we will research how design managers are dealing with the IP selection problem today. We will ask what IP they have selected, how they went about it and how the decision worked out.

After analyzing the data, we will present our findings in another special section of EE Times and in a panel session at the IP/SoC Conference in Grenoble, France, in early December. At that time, we aim to have a statistically significant picture of what the current industry practice actually is, which ideas seem to work and where the pitfalls lie.

We hope this effort will contribute to solving what has emerged as a profound challenge to progress in the development of system-level ICs.