The first question to ask in examining how design teams select intellectual property is who does the selecting. And just asking respondents about themselves gave us our first big surprise in the study. We sent out invitations to a cross-section of design and verification engineers and their managers. Normally, when we are studying a question that is not of great concern to managers, those busy folks will mostly not respond. But this subject was different.
It was not different in overall statistics, however. In fact, design team size — a mean of roughly 13 — was about normal.
Further, as we expected, the average size of designs appears to be creeping up: Our study found an average of 5.3 million two-input NAND equivalent gates. But it would not be accurate to say that IP selection is solely the problem of large system-on-chip designs. Fully a fifth of respondents said their most recent design was in the under-100k-gate range.
Nor is IP selection an issue only in high-volume designs. More than half of the respondents said they expected to ship fewer than 10,000 units of their chip. Many of those low-volume designs are probably targeted to FPGAs rather than ASICs.
That said, our respondent demographics were a dramatic departure from the survey norm. Hardware engineers, their direct managers and project leaders made up about 70 percent of respondents. But system architects — those elusive figures behind the curtain who rarely respond to any survey — and corporate managers together made up a quarter of the respondents, an unprecedented number.
The fact that architects and managers responded to our IP survey in unusually high numbers suggests that they are involved in IP selection to an unusual degree. But it doesn't prove it, since managers might have taken the time to respond to our questionnaire for any number of reasons.
Another question in our survey, however, was perhaps more telling.
We asked respondents to consider five categories of players: hardware engineers, engineering management, architects, corporate management and purchasing. Then we added two external influences: silicon vendors and the customer for the chip. We also defined, based on the results of focus group research, six phases of the IP selection process: identify requirements, identify possible candidates, make a short list, evaluate the IP, negotiate terms and conditions, and make the final selection.
We asked respondents to estimate the degree of influence (between "not involved" and "entirely responsible") exerted by each group during each phase of the process. The results, even allowing for the tendency of respondents to overestimate their own degree of participation, were striking.
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