Let's begin with the size of the chip design. If we just looked at the average — 5.3 million gates — we'd conclude that IP selection is a big-design issue. But averages can hide the truth. Calculating the median gate count, we get a strikingly smaller, 700k gates. The difference between the two is due mainly to the few percent of respondents who were working on designs larger than 20 million gates.

Peering into the detailed results, we find that nearly 20 percent of the reported designs were under 100k gates — small-ASIC and -FPGA country. Apparently, the use of IP has spread from huge systems-on-chip to significantly smaller designs (and, by extension, design teams).

So what kind of IP is going into all these chips? The range of functionality is quite remarkable. As one would expect, there are processors; something has to fuel the giant machine that is ARM Ltd. But there are also licensed DSP cores and a remarkable variety of specialized processing elements, including cryptographic processors, video codec engines and the like. Embedded memory elements are likewise common.

Also not surprising, given their difficulty of design, is the number of high-speed interfaces that are licensed. These include the whole range of networking and backplane interfaces and fast chip-to-chip links as well as various flavors of DRAM controllers — an area that is becoming a specialty in itself.

One surprise was the high usage reported for analog and mixed-signal blocks. About a third of respondents said they had used IP to implement clock generation circuitry, D/A and A/D converters, serializer/deserializers or physical blocks. Interestingly enough, IP in this category was much more likely to come from within the respondent's organization — between a quarter and half the time — than was the case for any other type of IP. So it appears that even when an organization has strong internal expertise in mixed-signal design, the tendency to reuse an existing core remains high.

Just as interesting as the types of IP cores used in a design is the number of instances of each type in the design. These figures suggest that the notion of the SoC as a board-level computer in miniature, with one CPU, some memory and a few peripherals, is outdated.

If the concept of multicore ICs sounds novel to Intel, it certainly isn't to these designers. Our average design — which of course is imaginary, lumping together architectures as it does — has 1.5 CPUs and 1.9 DSP cores. Adding in more-specialized processing units, the total for this category turns out to be an average of two processors per chip. Looking at the data another way, a quarter of all respondents reported more than one instance of microprocessor IP in their design. DSP cores seem slightly more likely to be used in combinations; about 40 percent of respondents who used them used more than one instance.

If memory serves . . .
The average design uses three instances of SRAM in the form of IP (presumably not counting SRAM embedded in other cores as caches, buffers and so forth). That's not too surprising. But another memory finding took us aback. Normally one thinks of embedded flash as being used — if at all — in a single, large block; but among the respondents who said they'd used flash IP in their design (more than a quarter of the total sample), over a third said they'd used more than one instance.

Complex interfaces are another area in which one instance just isn't enough for many applications. Our mythological average chip has two Ethernet controllers, slightly more than one USB port and two protocol controllers of other sorts. Perhaps influenced by very high-performance designs that are desperate for I/O bandwidth, the average chip has nearly two PCI Express ports and two DRAM controllers. Data converters also appear in multiples, with more than two each of D/As and A/Ds in the average reported design.

Generating clocks for all these blocks is no easy matter. Our average design has almost three delay-locked loops, phase-locked loops or clock generators on it.

It is useful to point out that our average chip appears to incorporate close to two dozen instances of reused IP. The design community has moved beyond the point where chip design — and remember, we are including a significant percentage of relatively small chips here — is primarily about writing RTL. Chip design is about IP integration, with new functionality increasingly filling in the interstices between the imported or reused blocks.

This is a profound change in the methodology — and one that, as we shall see, is not yet well-supported by either the design flow or the IP market itself.

 Gate count of most recent design

 Average number of instances