New and troubling I/O issues are cropping up as routers, switches, server blades and storage networking gear move toward 10-Gbit/s data rates and multi-GHz communications processors. And those choosing chip-to-chip and backplane interconnect technologies for these systems are finding some giga-ntic hurdles.

We explored this megatrend in interconnect design Nov. 18 in two Silicon Valley focus groups consisting of 16 engineers from a dozen companies. In addition, we conducted extensive on-the-record interviews with interconnect engineering managers from companies like Cisco, Hewlett-Packard, Lucent and Network Appliance. Finally, some material for this report was drawn from a panel discussion sponsored by Denali Software Inc. and moderated by editor at-large Rick Merritt.

A Cisco engineer in one focus group said mainstream hubs, routers and switches are shifting up from aggregating eight to 16 ports of 100-Mbit/s Ethernet to 24 to 48 ports of Gbit/s Ethernet. That's one driver of the Giga Era, and it's pushing a need for much higher I/O rates.

In computer servers, "our customers are asking for maximum computer power per floor tile," a Sun engineer told us. He described the rising flow of data from ever-faster networks and the coming generation of multicore microprocessors. Storage networking engineers face similar pressures, as networking and CPU speeds generate increasing flows of data users want to rapidly store and access.

Traditional parallel buses like PCI with separate clock and data lines are running out of steam in this race. As they widen, they become more complex and costly to route on a pc board, especially as system form factors shrink. And growing skew between clock and data lines has become increasingly difficult to resolve.

So, engineers have been turning to a host of high-speed serial interconnects with embedded clocking, seeking an integrated solution with simpler routing and more bandwidth per pin. But these serial interconnects bring their own challenges.

Engineers must evaluate a complex menu of at least half a dozen new interconnect standards. Many come in multiple flavors, and each presents its own set of trade-offs. We also found out that at multi-GHz rates, signals are creating new, strange and complex effects engineers have not yet learned how to measure and harness. Already engineers say the wired interconnects inside their fastest systems are becoming as difficult to tame as RF and microwave signals. The joke from the cell phone commercials-"Can you hear me now?"-is becoming the gut-churning refrain in the labs.

Once engineering managers decide how to proceed, they face an implementation labyrinth of make-vs.-buy decisions. Do they develop everything in-house, buy cores to integrate into their ASICs or FPGAs-a whole maze within the maze-or choose off-the-shelf silicon?

This special section is the first visible result of a six-month project that aims to capture intelligence on how systems engineers see these interconnect problems and how they are trying to solve them. Under the veil of anonymity, the focus group participants for this report spoke freely about their experiences. We will leverage their insights to develop a Web survey that will go out to a wider group of engineers and managers early next year. The results of that survey will be the centerpiece of the second and final installment on this topic in April.

Also in April, we expect to wrap up our project with an online Netseminar that will analyze what we have learned. Between now and then, you can keep track of the progress of this project online at http://www.eet.com/industrychallenges. The site will feature articles on how design teams are coping with the Giga challenge.

Our investigations so far have turned up three significant insights. The trend toward high-speed serial interconnects is raising the profile of signal integrity engineers who are becoming increasingly influential in the matrix of engineers and managers who make I/O design decisions. Chip and connector vendors are doing a poor job of filling the need for detailed simulation models of their components. And engineers are beginning to crib their score sheets in the complex race to determine which interconnect standards will be the strategic horses to back in their next-generation systems.

Also for this issue, we asked an industry analyst to share some of his insights on this topic. Jag Bolaria of The Linley Group (Mountain View, Calif.) sketches out the landscape of how he sees the interconnect challenges playing out today and tomorrow.

We welcome your feedback on this second installment in our Industry Challenge series. Tell us how the Giga era is affecting your world by dropping a line to editor at-large Rick Merritt at rbmerrit@cmp.com.