Westerhoff's team of a dozen engineers is responsible for understanding the RF-like signaling effects cropping up at giga speeds. The members teach hardware engineers how to handle high-speed designs. They oversee 3-D modeling of chips and boards. And they help choose board-level electronic design automation tools and qualify key semiconductors. Many are PhDs.

"We usually just call them the signal integrity engineers, but they are the ones doing the high-speed design and packaging now," said Bill Jennings, vice president of engineering for the division.

Westerhoff's team serves about 10 business groups in the division, providing specialists who sit on product design teams and provide them with key assistance, tools and training. A similar group serves Cisco's switching division.

The move from megahertz- to gigahertz-class designs has changed the nature of the I/O job, Westerhoff said.

"It's a paradigm shift that has significant impact on the tools and skills needed. We are smack dab in the middle of RF and microwave design, and the tools for those issues are different than the ones [we have been using] for digital board design," he said.

That's because the backplanes in the routers Cisco is designing today will need to stretch from 3 to 12 Gbits/s over the lifetime of the products. "Most senior hardware engineers working today graduated somewhere around 1990 when a 25-MHz 386 processor was a big deal. This is a totally different skill set," said Jennings.

Other companies are seeing the rise of a class of high-speed interconnect specialists, too.

"These days all designs go through a much more detailed review of I/Os," said Chuck McManis, a technical director at Network Appliance Inc. (Sunnyvale, Calif.), a fast-growing storage OEM. "We have a couple guys for whom [high-speed serial I/O] is their specialty. We don't ship anything without their signoff," he added.

In focus groups conducted Nov. 18, engineers representing a dozen systems companies agreed that signal integrity engineers are becoming key players in their interconnect decisions. "That's the most important person in my team, and the first person I hired," said an engineering manager with Hitachi Global Storage Technologies.

"My job has become easier in terms of the interactions I have," said a signal integrity engineer from router maker Juniper Networks. "Board designers no longer say [signal integrity work] is a waste of time and we are just delaying their tapeouts," she added.

That's because the once-arcane nuances of high-speed signaling are becoming central to whether a system works.

"We now have to deal with second- and third-order effects," said one engineer from Apple Computer Inc. in our focus group. "For example, the substrate length from a ball on a package to the silicon [can generate an effect]. You used to be able to ignore these sorts of things, but now they contribute to your first-order effects," he said.

"Serial interconnect technology is very much at the heart of the future of computers," said Michael Krause, an interconnect specialist in Hewlett-Packard's server group in Cupertino, Calif., the first company to launch backplane-based computer servers. "Backplanes will be a dominant theme in computer servers, in part to eliminate cables that still cause 85 percent of systems failures," Krause said in an interview.

These jobs include work on systems architecture issues.

"This is sort of what I do," said Byers. "I study the impact of technologies like serial backplanes on the evolution of our current systems and on potential new systems, and figure out their capacity, performance, reliability, power and cost implications.

"Certain new possibilities often emerge from this work, like the ability to use serial links on the backplane to enable a full-mesh interconnect, resulting in a system with 2+ terabits of backplane capacity in a single shelf," Byers added.

Systems architects are often the first stop on a journey through several engineering disciplines that are called on to participate in interconnect design decisions.

"We have a small group of elite people who work out the strategy," said another Apple engineer from our focus group. "They want to pick cores and chips that meet our needs across the whole product line. We've been in big trouble in the past when every system used a different chip set. That didn't make sense," he added.

At the highest level, marketing or product/project managers make broad decisions that influence the direction in I/O design, said an Emulex ASIC director in our focus group. "There are data sheet check-off features, and marketing makes sure you have the list of what they are," agreed an engineer from Hewlett-Packard.

"It's driven by performance," said a focus group engineering manager from Sun Microsystems Inc. "The architecture teams know what they want, they are aware of what's available and the road maps of the technologies. For us, marketing might supply a higher-level throughput or applications-level benchmark," he said.

At the opposite end of the spectrum, chip-level I/O designers hammer out some of the key details of interconnect design implementations.

"These folks are at the true cutting edge of transistor-level design, and need to really understand the semiconductor process parameters," said Byers of Lucent. "They work on the details of channel encoding, pre-emphasis and equalizer circuit design, drivers, receivers and clock recovery," he said.

The signal integrity engineers, for their part, "are always looking for that one extra inch of reach, or that incremental speed increase, or to better their channel bit error rate," Byers added. So they work closely with test gear suppliers to push the edge of new kinds of instruments and tools.

A final piece of the puzzle is the engineer who works on standards efforts. These engineers are always key in interconnects, where different devices need to interoperate, and they are especially in demand today.

"There is currently a flurry of activity on standardizing serial backplanes at rates over 10 Gbits/s," said Byers (see related story, page 37).

"If there is something proprietary in our systems, it is because there is nothing that meets our needs that we can buy," said Nader Vasseghi, a director of advanced engineering at Cisco. "In high-end routing most of the backplane work is still our secret sauce. In low-end platforms it's more useful to buy off-the-shelf parts and focus on other areas," he added.

Cisco still designs plenty of its own ASICs, often integrating interconnect cores it buys from third parties. By integrating serializer/deserializer, Cisco can lower the power and costs of the technology, but it must assume risks-particularly with relatively new and unproven high-end cores.

"Just as we have a library of memories and CAMs for our ASICs, we need a high-speed I/O library including serdes that we can integrate ourselves for our next-generation ASICs. Right now we face a lot of risks integrating 2.5 and 10G serdes," Vasseghi said.

Like Cisco, HP prefers to buy off-the-shelf parts, but it does design ASICs, too. When HP buys outside cores for those ASICs, engineers draft a detailed risk assessment based in part on the core provider's fab processes, design tools and volumes shipped.

For smaller companies, the need to leverage off-the-shelf components can be even more critical. "Most of us have a limited amount of people and we have to decide where to put our design manpower. We want to do the most we can with vendor silicon," said a systems architect from Force10 Networks Inc., a 5-year-old maker of switches and routers in our focus group.

See related chart