"There's a wide variance in the quality of the models we see. Some vendors do a good job of it and we trust their data, while others do a horrible job," said Todd Westerhoff, who manages a 12-person signal integrity team in the router division of Cisco Systems Inc.

"When you get to gigahertz speeds, the models for how an interconnect or a trace behaves become a big deal," he added.

"We don't think all vendors understand that these models form the basis of how we design in their parts."

Several senior engineers in our focus group said the lack of good models is a growing issue. One from Apple Computer Inc. characterized the problem as "huge."

In part, that's because the company sometimes makes design decisions based on a simulation model when silicon is still in the prototype phase, he said.

Engineers from Sun Microsystems Inc. said they have had to redesign the layout and other parameters for intellectual-property cores and I/O cells when board-level performance did not match silicon simulations. "Mostly the models don't match once the silicon is on the board," said one Sun engineer.

"You don't really know how accurate the models are until you have silicon," agreed a Hewlett-Packard engineer.

"You take it on faith and build it; then, later you go back to see where they screwed up," said a senior engineer from Nortel Networks Ltd. In the worst case, the problem could get elevated to the management level, affecting the relationship between the companies, he added.

One problem is that connector makers typically supply simulation models based on simple four-layer printed-circuit boards, even though most production routers and switches use much thicker boards, said a signal integrity engineer from Jupiter Networks. New and difficult effects crop up on the thicker boards, she added.

"It costs about $20,000 to get to a final pc board," said a senior engineer from Network Appliance Inc. "If it doesn't work because there is something the signal cannot get through, I am really irritated," he added.

What's worse, the problem cannot be solved by accessing information from a data sheet on the Web. Simulation models are often carefully guarded company secrets. Thus, a fix often involves multiple visits and nondisclosure agreement documents with the vendor.

"They make it painful," said the Network Appliance engineer.

One engineer went so far as to say his company has given up on simulation models. Ironically, in a recent panel discussion, representatives from Applied Micro Circuits, Intel, Rambus and Vitesse indicated they did not even know whether their companies provided any simulation models with their chips.

For its part, Cisco has developed a process for inspecting the simulation models for all incoming semiconductors. Once a part has been carefully characterized, its model is put into an in-house database other Cisco engineers can access.

In the gigahertz range, relatively long chip-to-chip interconnects become more predictable, but new short-range effects from connectors, vias and traces must be carefully modeled. Using frequency-domain circuit simulation and 3-D field solvers, Westerhoff's group at Cisco measures characteristic impedance right down to the level of a stub on a via that could make a signal ring.

"If you don't do this, the systems won't work," said Bill Jennings, vice president of engineering in Cisco's router group. "Three-D simulation modeling is no longer just for 5 to 10 percent of our designs. It's for 80 percent of them today," he added.

"Sometimes you look at a chip input and it looks bad and other times it looks good. It can be hard to tell. There is no sophisticated measurement or methodology to see it. It's a measurement problem to solve," said the engineer from Juniper.

For instance, at Gbit-plus rates, the roughness of a pc board can create "skin effects" that create irregular 3-D shapes on a copper trace and affect how signals propagate across the board. That's one reason that some engineers say they need 3-D, not 2-D, simulation models.

An Emulex Corp. engineer said that today's Ibis models are no longer adequate and that OEMs must demand more thorough HSpice models. "We have to drive it," he said.

One Cisco engineer said he is proposing his connector vendors do a full 3-D simulation at their site using the connector mounted on his OEM pc board. That lets the vendor protect the intellectual property that may be revealed in the model, but it effectively asks the vendor to set up a new testing business.

Another engineer said that some component makers are beginning to offer MatLab programs that provide an excellent tool for running a host of checks on the components.

"We need a common vocabulary and common acceptance criteria," said the Network Appliance engineer.

Problems get even hairier at the data level because most high-speed serial interconnects embed clocking information into the signal flow, making it hard to locate and test data packet flows. "You almost need a search engine on the tester probe to be able to find the strings of bits you are looking for," said the NetApp engineer.

"With serial streams, you are often working with sophisticated encoding, and it's hard to get a clear look at the signal," said an Apple engineer.

Westerhoff said Cisco is starting to use testers that offer both line testing of packets and oscilloscope-like functions for characterizing physical channels. Electronic design automation tools also must become better integrated, he said.

"The [interconnect] tool sets are relatively primitive and not well-integrated. We don't have fully integrated multi-GHz serial design tools yet. It's all point tools," he said.