Those are two of the conclusions from a panel discussion that was held in San Jose, Calif., in November as part of MemCon, which was sponsored by Denali Software Inc. Below is an abridged version of that discussion, moderated by EE Times editor at-large Rick Merritt. To hear an audio recording of the whole panel discussion, go to www.denali.com/memcon/sanjose2004_day2trackb_panel.html.

Rick Merritt: Jerry, what did you learn as a lead architect [at Intel] for Grantsdale, one of the first mainstream PCI Express chip sets?

Jerry Verseput: We wanted to attach Gigabit Ethernet to the chip set somehow, but it would end up being bottlenecked by PCI, so we knew that we needed to come up with something that was higher-bandwidth. At the same time [we needed something] for a chip-to-chip [interconnect] between our north bridge and south bridge controllers because we were also running out of bandwidth [there]. We came up with something that could serve both [needs]. That's when our corporate lab said, "You know what? This could be the next PCI," and it went from there.

The analog and the electrical difficulties that come up when you run at these [2.5-GHz] speeds pretty much require, at least for the first time, a series of test chips to make sure that that electrical interface is robust. The other thing that I think was surprising to some was that the transition to serial interfaces [did not] solve all of the component cost problems. At the same time that we were reducing the number of pins on a component, we were also quadrupling the bandwidth, which requires quadruple the buffers; so we shifted from an I/O-limited problem to a gates-limited problem, which was about cost parity. But now we're in a position where, from a component level, you can scale down those gates with process technology.

Merritt: What's the outlook for Express at Intel?

Verseput: Where we see [it] going now [is on] just about all the chip set components that we design.

Merritt: How is this Express transition going more broadly for the industry?

Al Yanes: From our perspective [at PCI-SIG], things are going well. As Jerry stated, Express is here. It's being widely adopted. We have plans in place to assist in its adoption, and we also have a good future road map to extend Express. We have a PCI Express 1.1 spec that will be released shortly with a bunch of fixes based on the two years of experience. We've found some holes in the specifications that we're fixing. In addition, we'll be announcing, probably in the first quarter, PCI Express Gen2-at least the data rates that we're going to be offering for PCI Express Gen2.

Merritt: Tell us about the debate over PCI Express Gen2 signaling rates.

Yanes: Well, basically, there's a camp that [wants] 5 GHz-it's simple and easy to do backward compatibility. There's another camp that says, "We'll need more bandwidth and 6.25 GHz. There are other specifications out that already do 6.25 that we can leverage." There are arguments on both sides, and we'll see what the smart guys in the [PCI-SIG] Electrical Working Group come back with.

Merritt: Is parallel PCI coming to the end of its life?

Yanes: We've seen vendors generate some PCI-X 2.0 533-MHz solutions, and we know that there's going to be PCI-X 2.0 266 solutions coming out. But based on how successful PCI Express has been, it's most likely the 533-MHz specification will be the last PCI-X spec the PCI-SIG generates.

Merritt: Sean, how do you see this transition to Express going, and what are the issues?

Sean W. Smith: From a logical standpoint, the complexity has really grown tremendously, and a lot of people are choosing to go out and look at IP solutions for both the physical layer and the digital or the MAC layer for PCI Express. There's a lot of confusion in the industry about how to integrate this into a device, how to test it, how to make sure not only that it's compliant, but that it works within the system [in question]. Verification has to step up and match that level of complexity.

The PCI-SIG has done a great job by trying to identify basic compliance suite testing . . . but it really does not answer the question, "Is this PCI Express device fully functional, and, more important, does it meet the requirements of my system in terms of how my system is going to perform in its target application?"

Merritt: There's a question now whether a very different version of an interconnect, called Advanced Switching, will be the right kind of solution for routers, switches and basestations, or if RapidIO, out of the Motorola PowerPC camp, is going to be better. What's your view, Sam?

Sam Fuller: Before I address that, I'd like to say something about PCI-X and Express: There's a system validation that's going to take place, especially in the server space, that I think will take a while, and I don't expect the server vendors to immediately deploy volume production of Express. So I think there's going to be a period of a year or a couple of years of needing to continue supporting PCI-X as well as PCI Express.

AMCC has PCI Express-based products targeted at the IT space. We also have PowerPC-based products in the communications space, and we have interest in Express there for peripheral attachment.

I've yet to hear a customer ask for Advanced Switching. I have heard a lot of them asking for RapidIO, though. It does seem to meet the connectivity requirements of that class of equipment much better than the kind of hierarchal bus structure of PCI Express. Advance Switching is still, in many respects, an unknown quantity.

The [overall] direction is definitely toward the use of encoded clock and data in multigigahertz systems where, if you have multiple lanes, they each have their own clock, and you have signal generation and recovery techniques on both ends. Once you've done that, you've clearly moved to a packet-based protocol as opposed to a multilayer handshake.

Merritt: When will AMCC deliver RapidIO connections on its parts?

Fuller: I wish it was sooner rather than later, but I think you'll see announcements in the coming year.

Merritt: Jerry, the case against Advanced Switching is that it is only the physical layer of Express with a lot of new stuff on top of it and few OEMs behind it. People say Intel doesn't really understand comms, but the company is just trying to nudge its way into that sector. What's the case for AS?

Verseput: The Advanced Switching interconnect SIG got started in December of 2003, and if everything goes according to schedule, we'll start seeing first bridges and fabric interface chips in 2005. So it's still in its early development stages. We're certainly seeing a lot of interest with the telecom equipment manufacturers as well as the silicon providers.

Advanced Switching fully reuses the electrical, physical and data-link layers of PCI Express and then, from Layer 3 on up, creates a peer-to-peer, packet-based protocol. What we're trying to do is take advantage of the economies of scale for the electrical layers, have something that can serve as your packet-based fabric and then hopefully create a kind of a seamless PCI Express chip-to-chip/Advanced Switching fabric.

Merritt: Kevin, you can't just use any 2.5-GHz underlying physical layer to do any of those protocols-you really have to do a very careful technical analysis of each one and make sure some of the details in that PHY design are correct. Is that right?

Kevin Donnelly: That's correct. Certainly, 2.5 gig is 2.5 gig, and they're all differential, so that's a great start. But there are a lot of details-in things like power-management modes, how they work, how they use their different levels of clock recovery-that make them slightly different. It does add a layer of complexity to try to combine these things. But in this era of uncertainty, people are trying to build chips that can handle multiple protocols, because when you commit to a mask you don't know where the market is going to be a year from now.

Speaking for the record
Jerry Verseput, director of technology and initiatives, Intel Corp. Communications Group

Al Yanes, senior chip set designer, IBM Corp.'s Engineering and Technology Services Group; president of the PCI-SIG

Sean Smith, verification engineer, Denali Software

Sam Fuller, vice president of marketing for embedded products, AMCC; former president of the RapidIO Trade Association

Kevin Donnelly, general manager, Logic Interface Group, Rambus