CMP's IP Selection Industry Challenge attempts to support these design managers in their efforts. With a combination of field research and analysis, we will establish how design managers are going about IP selection today. We will match results with practices to estimate which are the most successful techniques for IP selection. And we will report on the direction in which the graduallydeveloping IP chain is moving. We hope the IP Selection Industry Challenge gives design managers a clear view of what their peers are doing in this vital area, and a basis for moving forward.

IP selection
The semiconductor industry is entirely dependent upon the reuse of silicon intellectual property (IP) for the design of complex chips.

First, learn all the categories
Design teams take a huge variety of approaches to selecting intellectual property. That is clear from even a cursory conversation with IP vendors, even before any systematic data gathering.

Designers talk about fitting cores
The best way to find out how real design teams are selecting and evaluating intellectual property is to ask them. That is precisely what EE Times intends to do in the IP Selection Industry Challenges program.

QIP metric streamlines the process
In a perfect IP reuse world, one would simply connect a third-party intellectual-property block, validate the interface with the rest of the system and successfully produce fully functional silicon.

Building an efficient ecosystem
Today's intellectual-property ecosystem comprises several components and transactions, which have numerous interdependencies and challenges.

Designing ASICs for supersystems
During the past five years, ASIC system-on-chip design has taken on a new dimension — namely, that of ASIC SSOC (supersystem-on-chip) design.

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