This palette of options presents an interesting optimization problem to system architects. To work through to an implementation plan, they must have a firm grasp of their design requirements, the allowable trade-offs, and also a number of intangible issues that have less to do with the design requirements than with the skills and beliefs of the design team.

And they also need a clear view of the characteristics of each alternative-cell-based or structured ASIC, FPGA or standard-product. To that end, we offer the following summaries.

The simplest case is the classic ASIC vendor relationship. In this case, the entire NRE is negotiated with the ASIC vendor at the beginning of the project. ASIC-vendor NRE for a cell-based design will include charges for assistance in preparing and handing-off the design, charges for the back-end design work done by the ASIC vendor, license fees for intellectual property (IP) used, cost of the mask set and sample parts, packaging and test, and a premium based on the ASIC vendor's estimate of design and market risk. The final figure can run from under $100,000 for a mature process, such as 0.25- or 0.18-micron and a relatively simple design into seven-digit numbers for complex 130- or 90-nanometer designs.

An important point about ASIC vendor NRE is that it is part of a larger negotiation with the vendor. Other factors in the negotiation include unit price of the ICs, possible ASIC vendor rights to the design, the strategic importance of the design and the overall relationship between the ASIC vendor and the customer. Since the collapse of the Internet bubble, NRE has become quite flexible, and under some circumstances may be partially or fully absorbed into subsequent charges such as piece pricing.

The issue of cost for a COT design is much more complex. In place of the single relationship with an ASIC vendor, a COT design becomes a network of development partnerships, each of which involves a cash outlay.

Particularly in these days of leaned-down (or decimated) design teams, a COT design will usually involve design contractors. And when the chip is system-level, the design will almost certainly involve IP licensed from outside.

Thus, every aspect of the design can create its own cash requirement. Design contractors must be paid, IP license fees negotiated, test-chip masks and silicon purchased, final masks and sample wafers purchased, packaging and test services arranged, and, to be realistic, often failure-analysis work purchased as well. Rarely can any of these, with the exception of IP licenses, be amortized over the unit price of the finished ICs. So calculating the full NRE for a COT design requires a complete map of the design process, including contractor and partner relationships as well as foundry and assembly/test charges.

On top of the NRE components sits the cost of the work done by the design team itself. This also varies widely, depending on the amount of new design work involved, the ambitiousness of the design and the amount of work outsourced. But a reasonable rule of thumb is that a design that is a simple derivative of an existing, working IC will probably cost a few million dollars to complete. A startup designing an SoC from scratch, current industry wisdom holds, will spend at least $20 million in the process.

To begin with, you can reduce design time by reusing IP blocks-if you don't disturb them. But black-box IP is like Pandora's box: Once opened it, may end up lengthening design instead of shortening it.

Another important point to consider is that 70 percent or more of the elapsed time in the design cycle for a given block is spent in verification, not in design creation. So a block's complexity should be judged by how hard it will be to verify, not design.

An important corollary to this point recently emerged. You can substantially shorten the design cycle by doing less verification. On first glance, that sounds really stupid. But consider that in many consumer markets, the window for success may be a matter of a month or two. If you miss the window, the design is useless. So the risk of a longer design may actually be worse than the risk of an incorrectly functioning chip.

Particularly on such tight deadlines, foundry schedules can be important. Obviously you want to synchronize your tapeout with the foundry's shuttle schedule so that you will get samples back ASAP. But, recently, the major foundries have reported near-capacity operation for advanced processes. That may mean that even if you finish the design, you won't be seeing your first production ICs until you can get on the schedule.

Finally, the bane of SoC design is respins, which brings up granularity. The hard truth is that a minority of cell-based designs come out right the first time. This is a very biased observation, because the most challenging and complex designs are inevitably done in a cell-based methodology. Easy cell-based designs fare much better-in fact some ASIC vendors virtually guarantee first-time working silicon. But for hard designs there will be respins. If the errors can be corrected by simply changing wiring, the respin may be limited to one or a few metal masks, and may be reasonably painless-a few tens of thousands of dollars perhaps. If the correction involves changing the cell placement, it will be expensive and can, depending on the foundry schedules, take months.

Other risks are inherent in creating an SoC and are much harder to mitigate. Forecast risk is one of these. The NRE, tool investment and other design costs for a cell-based ASIC are high compared with any other approach. But none of these costs can be reduced if sales estimates are not met: they are sunk costs. The exception might be situations in which the design team has amortized the NRE or license fees over the product life. This, in effect, shares the forecast risk with the ASIC vendor or IP suppliers.

Forecast risk is not just a matter of good or bad marketing. As integration levels increase, SoCs become more and more specific to a particular set of features and performance level. You can't just change out one block on the chip if you guessed wrong on which communications protocol would be most popular-you have to redesign. So inherently, SoCs are more sensitive to issues that defy certain forecast, such as competing standards or popularity of features.

A further risk-little discussed in most circles-comes with the use of third-party IP. When a design team uses a piece of IP, it assumes the risk that the IP is actually the property of the licensor-that no other party's patents are violated by the design. If this turns out not to be true-an entirely possible outcome given today's totally fluid patent law-it is not the IP vendor but the IP user who is liable. The holder of a prior patent may not only have the IP vendor's patent set aside, but he may demand royalties and damages from a design team that has used the IP in good faith.

To deal with this, there are usually indemnity clauses in IP license agreements. They are, for the most part, worthless unless the IP vendor has sufficient assets to pay damages and royalties for all its customers, and to make good any losses in the user's sales that result from a highly publicized patent dispute. Few IP vendors could do that for a single important design, let alone all the users of a piece of key IP.

But then there are the rewards. A cell-based design can use less area, consume far less power and produce more performance than any other approach. It is, after all, near the ultimate in efficiency. Every transistor in the design serves a purpose, every memory is just the right size and every data path just the right width. The state of the art in design for performance and for power management can be employed. The most advanced processes-or most cost-effective processes-can be used. Functions that could not be integrated any other way, such as precision analog or RF blocks, can be included on the die.

If the combination of selling price and volume can justify the costs and risks, there is no better way to go.

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