Decision-making starts with a software-based behavioral model under the supervision of a senior architecture team, said vice president of platform technology Jeff Stockdale. The team's composition varies, he said, but at the moment it has about nine senior technical folks. All aspects of design are represented, with special emphasis on software technology.

Stockdale said the architecture team starts with a simple premise: Use off-the-shelf components whenever possible. That approach is based on the proven time-to-market and cost advantages of application-specific standard products (ASSPs).

The architecture team must be flexible in using this approach, since ASSPs are not always compatible. For the team, it also means continuous monitoring of the trade press to be constantly aware of new ASSPs as they are announced. "We watch off-the-shelf developments with a several-stage process,'' Stockdale said. When the architecture team spots something that might fit into a current or planned design, they do an intensive block diagram and functionality data-sheet review. If the cost-to-benefit ratio functionality and cost still appear to be a fit, the team will assign a hands-on evaluation of the chip in a prototype environment that simulates the intended use.

''This is to learn about the device and to validate the claims of the vendor,'' Stockdale said. ''We often find that while the performance claims are true under some specific condition, when you get multiple functions running simultaneously in complex parts you find memory bottlenecks, bus contentions and the like-things that limit the actual performance of the device to less than the data-sheet promises.''

This validation process has built up a lot of experience with various vendors, Stockdale said. "He suggested that some smaller ASSP developers may not be as careful with system-modeling issues as more resource-rich vendors, such as Broadcom, one of F5's primary suppliers.

That's a natural role for FPGAs. But Stockdale said F5 tends to rely on ASICs to implement these critical blocks. ''Our cost-of-goods targets won't tolerate putting all the additional functionality into one big FPGA,'' Stockdale explained. ''But our volumes put us right in that gray area where it's a tough call whether to go for FPGAs or ASICs. We have decided that by carefully managing front-end costs, ASICs are the better solution for us.'' In some cases small FPGAs will still be used for extremely volatile functions, such as interfaces.

This management entails a number of steps. First, amortizing NRE over a production run requires a solid forecast. ''We have enough history in this market to have our forecasts well-tuned,'' Stockdale said.

Second, using ASICs in moderate-volume applications requires extreme discipline in control of the NRE: low initial costs and minimal respins. To that end, F5 consciously tunes its architectural designs for implementation in a mature, relatively restrictive ASIC flow where performance is not on the bleeding edge. The company uses geometries larger than 130 nano-meters-thus minimizing both NRE and design risk-and works with a single, longtime ASIC partner on what is essentially an embedded array/structured-ASIC approach. The vendor provides base wafers with custom embedded memory blocks in addition to a sea of logic elements, which are then customized to F5's specs with metal masks.

That gives the company low initial costs, good turnaround and adequate performance. By rigid adherence to the strict design rules of this flow, F5 has minimized the risk of respins.

There is another benefit as well: F5 has tuned its design flow to incorporate an early prototype stage implemented in FPGAs. For the most part the FPGA RTL is used directly in the ASIC flow. The FPGA allows the engineers to functionally verify algorithms and features with real-world traffic (at reduced rates) while working toward netlist handoff to the ASIC vendor. In addition, the software development effort, springboarded off the software-only behavioral model, can move to the FPGAs for much faster verification runs. Further, software driver development can begin working with functional hardware much sooner and have the drivers nearly complete when the ASIC arrives.

That is F5's decision process in a nutshell. A team of senior architects selects off-the-shelf ASSPs and partitions the design to exploit the ASSP and to enhance it with a low-risk, inexpensive ASIC. The result is a line of popular and competitive IP traffic management boxes.