All of this points directly at an obvious choice: cell-based ASIC design. In fact, the vast majority of ICs used in disk drive assemblies are developed using cell-based methodology. But as Seagate Technology LLC's engineering director and lead architect, Mike Miller, tells it, obvious is not always optimal.

A case in point is a recent serial-attached SCSI (SAS) controller Seagate developed for use in its product line. ''Working with a new interface standard is a slow and laborious process,'' Miller said. ''The concepts of the interface are usually there early on in the process, but the details only emerge over time. So it's necessary to do chip development in parallel with the evolution of the standard.''

SAS was not an exception. ''The dual-port structure, frame sizes and delay specifications fell into place fairly early on in the development of the standard,'' Miller said. That gave the chip-design team enough hard facts to start work. An architecture that separated the interface and control logic from the read channel was chosen and design of the chip was started.

A lot of the blocks — and their verification benches — were simply reused from earlier cell-based designs, allowing the design team to concentrate on the one new area: the SAS interface. The Seagate team started out with a C-language model of the SAS protocol. This was translated into RTL and used to create an FPGA bridge chip that could go between an SAS host adapter and an existing disk drive.

While the bridge was useful for protocol debugging, it could do little to help with timing analysis and was in no way suitable for production, Miller explained. ''It was very large. The assembly stuck out six inches above the PC from an extra-long disk drive. And it never ran above 1.5 Gbits/second. Our target speed for the finished chip was 3 Gbits.''

Early in the design process the team began to look for alternatives to a conventional cell-based flow. The designers were fairly certain of being able to hit their power and performance targets with a cell-based design, but the new — and still evolving — SAS protocol was causing worries. ''You always have a few bugs in a parallel development like this,'' Miller said. ''It's almost impossible to verify interoperability until you have silicon in hand. So you really need to be able to make quick changes, resynthesize and spin the design quickly.''

That is not a virtue of cell-based ASICs.

Seagate's usual ASIC vendor, LSI Logic Corp., proposed an alternative that might solve the problem: its RapidChip Structured ASIC family. Because only top metal layers are used to implement user-defined logic in the RapidChip family, it is possible to respond to changes significantly faster than with cell-based designs. ''It appeared to us that we could spin the design four to six weeks faster this way than with an all-layers approach,'' Miller said.

The problem was that the RapidChip family includes only a few specific master slices, with prediffused interfaces, memories and, in some cases, processors. None was ideal for Seagate's design, and in any case Seagate needed to reuse its existing intellectual property blocks to meet the schedule.

LSI proposed a novel solution. Why not use the RapidChip methodology, but create a base wafer designed around Seagate's IP blocks? The initial design would be, in almost all respects, a cell-based design. Seagate's existing IP would drop into the chip and the new SAS interface logic would be implemented in a sea of metal-configurable cells. If the RapidChip approach worked, the design could be taped out as a RapidChip base wafer, allowing fast respins. If the RapidChip layout couldn't meet timing or power, the chip could be completed and taped out as a conventional cell-based design.

The large savings in nonrecurring engineering costs that normally would accompany a Structured ASIC design wouldn't be there, nor would the shorter initial design cycle. But the possibility of being able to implement changes in the SAS logic with just some metal masks was enough to convince Seagate.

''The first-level project manager made the call, based on the analysis done by his design team,'' Miller said. ''He presented a solid case to his management and we went with it.''

The move was probably made possible by the culture of controlled turmoil that is the storage industry today, Miller said. ''The ASIC design team picks up blocks from functional platform design groups — servo, read/write and so on — and fits the functionality into the market requirements for a particular drive family. It's an environment where over time you can count on everything changing; you get used to that. So the team is always looking for a better way to do things. Skeptical, but open minded.''

The design proceeded pretty much along cell-based lines. ''We placed the transceiver cores, memories and other major blocks using the floor-planning tools we normally use,'' Miller said. ''We have learned that the floor planners are good at some things and not others, so we didn't have big surprises there.''

From a workable plan the team went into synthesis and layout. ''We weren't really sure about the timing until we were in the early stages of synthesis,'' Miller said. ''We kept the option of a fully cell-based design open right up until we released the design for the RapidChip slice.'' But in the end, the team had a good experience with timing closure using the logic fabric, Miller said. ''And we found that we could in fact resynthesize rather quickly.''

Power had also been an initial question, but this too proved to be acceptable. ''The power is similar to what you would get from a high-performance cell-based design,'' Miller said. ''That was crucial, because the die had to be able to work in the low-cost package we had planned for production.''

Overall, Miller said that the only major change in outcome from a fully cell-based design was a slight increase in die area. In exchange, Seagate benefited from the simpler flow and easier modification on the critical SAS interface. Miller said that this may have accelerated the design schedule by two full quarters.

By taking the concept of an IP-rich master slice and applying it to one company's internal IP portfolio, Seagate was able to use the infrastructure LSI had built up to support RapidChip, but with its own proprietary blocks. This led to many of the advantages of an existing platform chip, but with the critical flexibility to hit the moving target of an evolving standard. More than an endorsement of any particular ASIC product line, Seagate's experience with the SAS controller is an object lesson in the importance of having a design team that aggressively seeks new alternatives, weighs them carefully and then moves fast.