No one design could be representative of the activity today in highly integrated systems development. Systems designs that met our criteria appeared all across the applications spectrum. They showed a huge variety of thinking in partitioning and implementation. But the statistics are fascinating, and they conceal some interesting generalizations.

To begin with, applications. Every one of the application choices we listed on the questionnaire was represented in the results, including activities we normally don't think of as U.S.-based designs: consumer electronics, for example. Some segments have become quite narrow: military, defense and aerospace made up about one respondent in 30, and automotive, despite the huge attention it receives from some standard-product IC vendors, barely one in 20.

Others were surprisingly healthy. Despite the well-publicized death of the communications industry, two of the four most-reported application areas were wired and wireless communications/networking, at about 15 percent each. Computer systems and peripherals were right there, too, making it a three-way tie for second. The leader, by a statistically significant margin, was the cluster, including industrial controls, test and measurement equipment — the traditional foundation of the U.S. electronics industry and once again, apparently, its largest component.

Not surprisingly, the latter segment had more small companies than the overall industry, and tended to have lower expectations about shipping volumes. These factors will show up again later in the design choices engineers in this segment make. Even less surprising, the consumer electronics and computer industries tended to have above-average shipping expectations.

The total number of gates involved in the design also showed some interesting patterns. Most discussions on the subject suggest that gate count is normally distributed, with a markedly higher number of designs using quite moderate gate counts. This argument is frequently used to explain how FPGAs, despite their physical limitations, will soon take over the world. But the data does not support the assumption. Rather, our respondents described a rather flat distribution, with similar numbers of respondents reporting gate counts in the bins of under 100k, 100k to 500k, 1M to 2M, 2M to 5M and over 5 million gates. Curiously, the bin in the middle, 500k to 1 million gates, was the smallest.

There was a close relationship between the three distributions for gate count, company size and expected shipping volume. It would appear that, as a generalization, larger companies playing in high-volume markets tend to opt for higher levels of integration.

How those gates get used is an important issue. Most of the designs reported used about 20 percent of their gate count for memory. But the average was pulled up by significantly higher memory content in designs implemented in cell-based ASICs or gate arrays. Logic functions used just under half the gates in most designs.

All over the map
About a third of the designs overall included no analog or RF content, and half said these functions made up less than 10 percent of their design. The latter number shot up, interestingly enough, to almost two-thirds of designs that employed FPGAs or gate arrays having little or no analog content. But here there was a small but interesting contrary view: The small number of users who reported that greater than 60 percent of their design was analog or RF were also likely to use FPGAs.

Given the variations in application and gate count, it's no surprise that maximum clock frequencies used in these designs were all over the map as well. Here, the bulk of designs tended toward the low end of the spectrum, with the overall median frequency at only 199 MHz. But going fast is not an elite activity: about a sixth of respondents said their designs included circuitry running at 500 MHz or more.

As one might expect, designs employing FPGAs had a lower median clock frequency than those using cell-based ASICs. More surprising, designs employing large off-the-shelf ICs or ASSPs had similar numbers. Even more surprising, designs employing structured ASICs had a higher median clock frequency than any other group.

Remember in puzzling through these results that many respondents used more than one implementation technology. So, for instance, a design reporting a 2-GHz maximum clock frequency could have been using a 2-GHz Pentium sitting next to a board full of 50-MHz FPGAs.

Finally, let's take a statistical look at what functions went into these designs. As previously mentioned, memory plays a huge role in hardware design these days. Over 80 percent of respondents said that they used some form of RAM in their design, and nearly half used some form of nonvolatile memory. The data provides a nice hint about the makeup of the RAM component: a quarter of respondents employed a DDR DRAM controller, often in a cell-based ASIC.

Next after memory comes processors. It almost goes without saying that most designs are CPU-centric these days. And, in fact, about 70 percent of respondents said they had at least one embedded processor in the design. Separately, about a third used some form of DSP chip or core. Interestingly, DSP use seems most frequent in designs that were implemented using either ASSPs or structured ASICs.

Here, then, is a statistical snapshot of today's complex designs. If there could be an average design, it would have a CPU and both conventional RAM and nonvolatile memory. It would run at around 200 MHz and altogether consume the equivalent silicon area of couple of million gates.

But there is huge variation around that ''typical'' point, often in areas that are very significant: the highest-volume designs tend also to be the most complex, for instance. These are the targets our respondents are trying to achieve with their implementations.

See related chart

See related chart