The seminal question of this study was how design teams were implementing the systems they were creating. Vendors of course wanted to know so that they could refine their marketing programs. More importantly, working designers and design managers needed the information so they could make their own decisions using a wider base of experience. In this regard the study has a lot to say.

The implementation question really has two components, each relating to a different phase of system design. One component relates to the early portion of the design process: Where does the detailed design come from? Here we will look at the role of third-party intellectual property (IP) in our area. The second component relates to the implementation of that design: What kind of silicon does the design team turn to — ASICs, FPGAs or standard-product ICs? We will examine each alternative in detail.

First, let's look at IP. The prevailing wisdom has been that you can't complete a modern design without relying on some sources of previously developed IP. In fact, a slight majority of our respondents said that they used no third-party or internal IP in their design work. Even though this response may be somewhat dependent on what you define as IP — such as a rework of a design that already exists — this is a blunt repudiation of the IP dogma. Most designers don't buy it, so to speak. The use of IP does appear to track with increasing design size, however, so as designs continue to grow there may come a point in the future where the majority of designers will be using it. We shall see.

Those who do use IP show interesting patterns. The most widely used IP blocks are embedded processors and RAMs. In fact, the number of respondents saying they used embedded processors at all was just over twice the number saying they used processor IP, so it appears that about half the processor users license their cores and the other half roll their own. The spread is larger with DSPs, with reports of DSP IP use running just over one-third of the reported total of DSP uses.

Another category of IP cores was mentioned frequently as being reused: the nasty high-speed or protocol-dependent stuff. This set included serializer/deserializer cores, double-data-rate DRAM controllers, data converters and the aging but ubiquitous PCI controller.

The second step in our investigation was to see how designers implemented their systems. This is the part where a lot of chip vendors are holding their breath. And the winner is . . . all of the above, in an unbelievable range of combinations. When we asked respondents how they partitioned their design, there was on the average about 1.5 responses per individual. That is, the mythical average design used two different technologies in combination. Not a lot of purists out there anymore.

Lots of FPGAs
The most commonly used technology was, by a wide margin, FPGAs, used by nearly two-thirds of respondents. The devices were used not only by themselves, but also in combination with each of the other alternatives. It is probably fair to say that the FPGA has become the staple food upon which the design diet is constructed.

Second most common was large, off-the-shelf functional chips or application-specific standard products, at just over one-third of respondents. Not surprisingly, given their cost implications, use of both FPGAs and ASSPs plummeted with increasing shipment volume. At high volumes, the No. 3 option, cell-based ASICs, was dominant. They were mentioned by just under one-third of respondents overall.

Newer technologies and older technologies brought up the rear. Structured or platform ASICs made a credible showing at about one respondent in seven. Gate arrays and the emerging technology of ASSPs with embedded FPGA blocks came in at the tail end.

Peering into the detailed data, it appears that when a design team chooses an ASSP or other large off-the-shelf chip, the members look for a very good fit between the functionality of the device and their overall needs. Users of ASSPs reported significantly fewer-than-average uses of the other technologies. Additionally, despite conventional wisdom, it is not that common for design teams to use FPGAs in conjunction with cell-based ASICs, probably for the same reason. If the team is going to the trouble and expense of a cell-based design, it will put everything it might need inside.

We have seen the patterns of IP use and of partitioning decisions in the market today. The picture is one of pragmatic engineering, if the phrase is not redundant. Design teams pick the technology, or combination of technologies, they need to get the job done. Our final step is to take a look inside those decisions.

See related chart

See related chart