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IP99 Europe newsNov.1-2, 1999 EICC Edinburgh,United Kingdom IP99: Simutech, ISS evaluate a core via the Web(11/03/99, 4:44 p.m. EDT)EDINBURGH, Scotland ý The first functional verification of an intellectual property (IP) core over the Internet was demonstrated this week at IP99 by Simutech LLC (Vancouver, Wash.) and Integrated Silicon Systems (Belfast, Northern Ireland), using Simutech's Rave prototyping system. IP99: ASIC vendors warned on rise of core providers(11/03/99, 3:38 p.m. EDT)EDINBURGH, Scotland ý A steady rise to power of third-party developers of intellectual property (IP) will bring pressure on ASIC vendors, which have heretofore been the traditional leaders in system-level integration, according to two keynote speakers at the IP99 Europe conference and exhibition. Seiko Epson joins Alba project in Scotland(11/03/99, 1:10 p.m. EDT)LIVINGSTON, Scotland ý Seiko Epson Corp. will locate a design group at the Alba system-on-chip (SoC) design campus in Scotland, making it the third company to commit to opening an office there. IP99: Stellar and Sican team up on cores(11/03/99, 10:38 a.m. EDT)EDINBURGH, Scotland ý Two providers of intellectual property (IP) cores, Stellar Semiconductor Inc. (San Jose, Calif.) and Sican GmbH (Hannover, Germany), announced a marketing and sales agreement at the IP99 Europe conference and exhibition. IP99: panel raises pay-to-evaluate IP issue(11/01/99, 5:59 p.m. EDT)Without providing definitive answers regarding business practices involving intellectual property (IP), a panel discussion hosted by the Virtual Components Exchange (VCX)at the IP99 Europe conference and exhibition served to highlight the issues, differences of opinion, and opportunities that exist in the emerging semiconductor IP industry. Industry rallies to trade IP online(4:00 p.m. EST, 11/1/99)LIVINGSTON, Scotland? The promise of easy access to intellectual property (IP) cores over the Internet will come to the IP99 Europe conference here this week, as catalog providers and standards bodies announce they are collaborating on a new standard for exchanging IP information. The idea is to let a user issue a single query that's automatically routed to multiple catalogs and IP suppliers, greatly simplifying what today can be an arduous search. Europe's chip makers take varying paths to reuse(9:00 a.m. EST, 11/1/99)"Reuse requires an architecture and discipline," he said. "We can't force an architecture for all applications and we can't force such a discipline on so many groups, so we developed the application- specific platform." The software is developed to define boundary conditions, according to the Trimedia software system architecture (TSS), which allows the same software to be used on either a MIPS processor or a Trimedia processor and still handle streaming applications in real-time. "The switches are invisible to the developer. They are not yet automatic, but they are reasonably straightforward," he said. How National crammed 43 functions into one Geode(9:00 a.m. EST, 11/1/99)Here's the problem. You have been asked to integrate all the functions for a loosely defined device-the Internet appliance-into one chip. The 43 functional blocks you need are available, but must be drawn together from eight design teams at what were four companies spread across five locations worldwide. The designs have been done for different manufacturing processes and are expressed at various levels of abstraction in several different database structures. You have nine months to turn a product definition into physical samples in hand. Go. Title Hardware/software co-design powers system-chip(9:00 a.m. EST, 11/1/99)With a growing majority of system-on-chip (SoC) functionality existing in software, hardware/software co-design and co-verification are becoming essential methodologies for creators and integrators of intellectual property (IP). Tools for co-verification are being deployed with some success, though designers say help is needed in such areas as processor support and verification speed. Babel of languages competing for role in SoC(9:00 a.m. EST, 11/1/99)To design a multimillion-gate system on a chip with multiple intellectual-property blocks, one must work at a high level of abstraction, and there is a growing consensus that today's HDLs are not up to the job. But here is where the consensus breaks down, as advocates of C/C++, Java, SDL, Superlog and other approaches debate the merits of their proposals. Most recently, the momentum appeared to be swinging behind the C++ class library approach as the Open SystemC initiative launched in late September by Synopsys and CoWare claimed over 50 intellectual property (IP), EDA, semiconductor and systems vendors. But even that list includes startups with their own language approaches, and there are significant companies and standards bodies that are forging their own paths to system-level design.
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