IP TRENDS: THE SOFTWARE CHALLENGE

To design a multimillion-gate system on a chip with multiple intellectual-property blocks, one must work at a high level of abstraction, and there is a growing consensus that today's HDLs are not up to the job. But here is where the consensus breaks down, as advocates of C/C++, Java, SDL, Superlog and other approaches debate the merits of their proposals. Most recently, the momentum appeared to be swinging behind the C++ class library approach as the Open SystemC initiative launched in late September by Synopsys and CoWare claimed over 50 intellectual property (IP), EDA, semiconductor and systems vendors. But even that list includes startups with their own language approaches, and there are significant companies and standards bodies that are forging their own paths to system-level design.

However, the need to move on is clear. "When we talk to designers, we hear over and over again that HDLs have run out of gas," said Brian Barrera, director of strategic marketing at Synopsys Inc.'s system-level design business unit (Mountain View, Calif.). He noted that systems and software architects are already working in C/C++ and that 50 percent to 90 percent of system-on-chip (SoC) functionality is now defined in software.

If hardware architects worked in C/C++, Barrera noted, it would be easier to co-design hardware and software, and system functionality could more flexibly be moved between hardware and software for derivative designs. Additionally, he said, SoC hardware designers need simulation performance not available with VHDL or Verilog.

A growing number of design managers agree. "C is almost universally known, but HDLs are only known by hardware engineers," said Pierre Coulomb, systems architect and project leader for STMicroelectronics' wireless communications unit (Grenoble, France). His unit is using C/C++ for high-level descriptions of hardware blocks, which are refined using the N2C co-design tool from CoWare.

Alcatel Microelectronics (Brussels, Belgium) is looking into C/C++ design with pilot projects, said Marc Genoe, CAD manager. "Specification in C/C++ is starting, and we would like to move in that direction for sure," he said. Genoe said he hopes that this will bridge the gap between system engineers and hardware engineers, as well as provide a way to write test benches at a higher level.

Whether hardware designers will actually move to C/C++ remains to be seen. The more immediate benefit of a standardized C++ class library, whether provided by SystemC or the competing CynApps CynLib proposal, will be to allow IP providers to issue cores in a standard dialect of C/C++ for rapid evaluation.

But C++ can't do it all, said Stan Krolikoski, senior architect of the system-level design group at Cadence Design Systems Inc. (San Jose, Calif.). "When you're talking about something as complex as an SoC, there are a number of possible languages you might want to use," he said. For example, he said, designers might use UML for top-level design specs, C/C++ for a test bench, SDL for protocol stacks, Signal Processing Worksystem (SPW) for data flow and so on.

The multilingual approach is a hallmark of the System-Level Design Language (SLDL) Rosetta effort, now a project of VHDL International (VI). In its first phase, Rosetta is envisioned as a constraint language that can work with multiple functional languages, including perhaps C/C++, Java, SDL, Superlog and others. Phase 2 will support a behavioral capability, but this is not intended to replace existing languages.

"Nothing exists out there to handle constraints, which can become very complex in SoC design, and nothing supports the ability to mix and match across different modeling styles that will be used in upcoming SoCs," said VI president Steve Schulz. "Rosetta seems to be unique in its ability to talk about multiple views of a system all together and to verify formally that all views are satisfied by an implementation."

Arnout: C needed to involve software team

Progress is under way in both phases of the Rosetta project, with a new team, the Systems Semantics working group, diving into Phase 2. The team is working on a "semantic backplane" that will define how to communicate with new and existing languages.

C++ class libraries could become part of Phase 2, but Schulz is concerned that the current open-source standardization efforts may be putting the cart before the horse. "Most C efforts are constrained to digital only, simulation only, static-concurrency only and behavior only," he noted.

The SLDL approach has impressed Chris Lennard, chair of the system-level design development working group at the Virtual Socket Interface Alliance (VSIA). "The reason you must always deal with a heterogeneous environment is that everything exists in legacy, so Verilog, C/C++ and Java are already going to be out there. The key critical component is how these things actually communicate," he said. "My feeling is that the SLDL approach is the way to go."

By any measure, Rosetta is a few years down the road. In contrast, the Open SystemC initiative is presented as a solution that can help as early as next year by defining a standard C++ dialect that can be used not only for IP modeling, but as a platform upon which to construct a new generation of synthesis, verification and co-design tools.

Both SystemC and CynLib are open-source C++ class libraries with simulation kernels. A class library lets programmers define hardware concepts missing from C, such as concurrency, clocks, ports and reactivity. Startup CynApps (Santa Clara, Calif.) doesn't have as long a list of endorsements as Synopsys, but its CynLib library has won support from Cadence, Cisco, Magma Design Automation, Mentor Graphics, Sun Microsystems and others.

"There are a number of competing approaches to system-level design, but the only realistic candidate in the context of SoC design is C++," said Synopsys' Barrera. "Proprietary languages do not easily connect with C/C++, the de facto standard languages for systems and software development. Proprietary extensions to C are not appropriate, because they lock you into a single supplier."

"A modern cell phone runs a million lines of code," said Guido Arnout, president and chief executive officer of CoWare Inc. (Santa Clara, Calif.). "If you want to move hardware into software, the next language has to be C-based, or the software guys will not participate."

Though CoWare itself has some proprietary extensions to C, the company agrees with Synopsys that a standardized C++ class library is essential. Indeed, it has been a major participant in the Open SystemC effort. "A class library structure that becomes standard is ideal, and an open standard could provide concurrency, clocking, asynchronous behavior and multiple clocks and gated clocks," said Arnout.

"The issue is that if we agree on a common dialect, it's much easier for people not only to develop models but also to exchange and reuse them," noted Barrera.

IP providers seem to agree, given that ARC, ARM, Billions of Operations per Second (Bops), Integrated Silicon Systems and MIPS are among the vendors that have indicated their support of Open SystemC.

"ARM is pleased that Synopsys, CoWare and other companies have come together on SystemC, because if it is taken up by the industry, it simplifies our world," said Tudor Brown, chief technology officer of ARM Ltd. (Cambridge, England). "The bane of the modeling world has been the large number of languages and approaches that are available."

But synthesis from C/C++ is not necessarily the driving goal of the Open SystemC initiative, and it may not be practical for some time, Brown warned. He's not alone in that view. "There have been several attempts in the past at high-level synthesis, but it hasn't really worked," said STMicroelectronics' Coulomb. "It would be of value, but it's a very difficult problem."

Other companies pushing a C language methodology are warming to the C++ class library approach. For example, Frontier Design Automation Inc. (Leuven, Belgium) uses C++ classes to encapsulate fixed-point data types for its A/RT (algorithm-to-register transfer) tool suite. The company is one of the Open SystemC backers.

"The use of C in general has problems, but C is well-suited to the DSP problems we are trying to solve," said Dave Koons, vice president of engineering for North America for Frontier. He uses the A/RT tools to design DSP and wireless IP.

C Level Design (San Jose, Calif.) takes generic C as input and uses "algorithmic synthesis" to reduce it to an RTL description. "We have a style for writing C where we're relying on C ordering to give concurrency," said Martin Baynes, vice president of engineering. "We guarantee that if you write to that style, it will be 100 percent cycle accurate to VHDL and Verilog."

Baynes acknowledged that using pure C for hardware design can require a lot of function calls. He said C Level Design plans to support C++, but hasn't yet signed on to either SystemC or CynLib. "Most of the solutions we've seen take RTL up to the C++ realm. They have not been open environments for supporting synthesis from C++," he said.

Standing in opposition to C/C++ advocates are those who say a fresh start is needed. Among the most vocal is Co-Design Automation (San Jose), which, perhaps surprisingly, is one of the Open SystemC backers. But Simon Davidmann, Co-Design's president and CEO, made it clear that his company will support C++ for legacy IP but thinks the company's new Superlog language is the real answer.

"There are two directions being pursued," said Davidmann. "One is trying to move HDLs into the systems domain and the other is trying to move algorithmic stuff into the hardware domain. There's merit in both, but I believe Superlog encompasses the best of both.

"You can take things from C and add libraries and you can model systems," Davidmann said. "But I don't believe a class library is going to give you all of the fundamentals you require." Proponents of C/C++ aren't being quite honest, Davidmann said, because a system-level language has to encompass design, software and verification as well as modeling.

C Level's Baynes noted that Superlog is owned by one company and is in danger of becoming a "proprietary language." SoC designers would still need a bridge between C and Superlog because software development will continue to be done using C/C++, he said.

There are many other approaches to system-level languages, some of which are under evaluation by an Open Verilog International (OVI) architectural language subcommittee. But Co-Design is not offering Superlog as a candidate. Nor is the Open SystemC initiative presenting its proposal to the OVI committee, which is seeking to endorse a new standard.

One company working with the OVI committee is LavaLogic (Columbia, Md.), which is pushing Java. "As far as we know, Java is the only language that allows you to infer directly without elaborating the code or adding special class libraries to the language to extract parallelism," said Bob Barker, vice president of marketing.

Simulation Magic (Cupertino, Calif.), also represented on the OVI committee, sees its graphical C-based language as the answer. "Our approach lets you model a system in a week, by providing a library of IP objects and a graphical engine that's easy to use," said president and CEO Shay Ben-Chorin.

Arexsys (Grenoble, France) is pushing its SDL-based Archimate co-design prod-uct, but also supports Open SystemC. Francois Constant, president, said the firm intends to output architectures to the SystemC class library.

Though Cadence has conducted a research effort for a language called Esterel-C, that company's Felix co-design initiative will work with multiple languages, Krolikoski said. "If a language is adopted by the market, we will support it," he said.

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