In this subwavelength regime, IC features printed on the silicon wafer are not an exact representation of the physical design as represented in the GDSII data format. Optical distortions and other process effects deform the patterns

imprinted on the reticle, contorting rectangles into rounded, hourglass shapes and causing very fine features to fade away altogether. The outcome can be a chip that performs off-spec-or not at all.

RET compensates for these effects by modifying the original GDSII data to enhance the contrast on the wafer of subwavelength mask features and to offset edge-deforming distortions. These enhancement techniques can yield astonishing reductions in critical feature sizes using existing 248-nm, deep-ultraviolet (DUV) stepper wavelengths. Under laboratory conditions, for example, RET has successfully created individual polygate features as small as 25 nm, one-tenth of the wavelength of light used to expose them. But hero experiments on isolated gates are one thing: subwavelength design and fabrication of actual high-density ICs containing millions of transistors are quite another (see Figure 1).

At Motorola, we have successfully applied a combination of phase shifting and OPC to shrink the transistor gates of functional, production-level chips containing significantly more than 10 million transistors, achieving significant reductions in gate sizes and a corresponding improvement in chip yield and performance. Using phase-shift and OPC tools, we have consistently fabricated products with average gate lengths of less than 100 nm using 0.18-micron process technology and a stepper wavelength of 248 nm.

Our work has conclusively demonstrated the viability of RET as a post-layout solution to the limitations imposed by subwavelength effects. However we have also learned that effective application of RET in the subwavelength regime requires a more comprehensive flow of information between designers and fabs. Moreover, to reap the full performance-enhancing benefits of RET, these processes must be integrated throughout the design-to-fab infrastructure from cell libraries to silicon.

The two RET techniques used most-phase shifting and OPC-modify the physical layout in two very different, but complementary, ways. In addition, each of these may exist in fundamentally different implementations, such as model-based and rule-based. OPC works to preserve the fidelity of critical layout features by counteracting the predictable edge distortions of subwavelength shapes (see Figure 2), whereas phase shifting enables smaller features to be printed on the wafer by enhancing the contrast of imaged light patterns.

OPC minimizes subwavelength edge distortions by changing the GDSII, adding small features such as hammerheads, edge-offsets staircasing, and serifs to the polygons drawn on the original layout. Reticles generated from a GDSII that is modified in this way will generate patterns on the silicon that more closely resemble what the designers had intended. The process therefore enhances the printability and accuracy of patterns on the wafer, which improves the reliability of chip performance as well as the yield.

At Motorola, phase shifting is done using a lithographic process called alternating-aperture phase-shift mask (AAPSM). In our version of this technique, the polysilicon level is double-exposed using two masks that are successively imaged onto one lithography level and onto the same resist layer. With this method, phase shifters are added to one mask on either side of a critical feature, such as a polygate. The shifter changes the phase of light passing through it by 180 degrees, while on the side-without a shifter-the phase change is zero degrees. During wafer exposure, the oppositely phased light images destructively interfere with each other, forcing the electric field vector to be zero at the center of the image and boosting image contrast on that particular region of the wafer resist.

The higher image contrast enhances resolution far beyond what is possible with traditional binary masks, allowing the creation of smaller features (see Figure 3). The second exposure uses a conventional binary mask to cut away unwanted polysilicon that cannot be removed by the phase-shift exposure. It's also used to define routing polysilicon, to square off gate ends, and so on.

The two exposures therefore define two new GDSII layers created from the original GDSII, neither of which resembles the final silicon or the original physical design. Moreover, subwavelength strategies introduce new constraints on exposure and design rules that require sophisticated algorithms to manipulate the original design and produce the desired result. Doing this for a large design without errors and in affordable computer time demands the novel, hierarchy-driven software incorporated in design tools such as those supplied by Numerical Technologies, Inc. (San Jose, CA).

It also requires additional design rules, which guarantee that circuit blocks can be corrected downstream without conflicts.

Trimming dimensions

When used together as part of a comprehensive reticle-enhancement strategy, phase shifting and OPC can reliably trim the dimensions of critical IC features, substantially boosting chip performance and yield while simultaneously extending the useful life of existing 248-nm production equipment. For IC designers and manufacturers who must stay ahead of the curve of shrinking features and growing chip complexity, subwavelength-processing methods offer an effective and practical new paradigm from which to work. But like all new paradigms, the subwavelength regime plays by a different set of rules from the old paradigm.

The chief disparity between the new subwavelength paradigm and the conventional superwavelength one is that the old adage of "what you see is what you get" (WYSIWYG) no longer applies. In other words,unlike before, features drawn on the physical layout at tapeout differ markedly from the subwavelength patterns created on the mask, which also look very different from what actually prints on the wafer. This is a direct result of subwavelength effects and the reticle enhancement process, in which the GDSII undergoes fundamental modifications to ensure that subwavelength features print as correctly as possible on silicon. These techniques also permit critical features such as gates and bit-cell polysilicon to be printed at dimensions way below wavelength for speed and density enhancement.

Phase shifting and OPC must also be carefully implemented according to a unique set of process rules. For example, when applying OPC to phase-shifted features, care must be taken to avoid exceeding the printable limit of the resist or the capability of mask inspection tools. The phase shifters themselves must meet certain minimum size and separation constraints, too. Proper distances must be maintained between each phase shifter as well as neighboring features on the layout. If a shifter should stray too close to a neighboring feature or another shifter, it will create a "phase conflict" if the two neighboring shifters are of opposite phase (see Figure 4).

Some layout shapes present intractable phase conflicts. A T-junction, for example, is nearly impossible to phase shift because no matter how the phase shifters are positioned, one segment of the T-junction will not border oppositely phased shifters and its silicon image will blur.

Subwavelength control

Controlling and monitoring all these subwavelength processes through the conversion from binary mask to AAPSM understandably contributes to the cost and complexity of mask making. But the gains in chip yield and performance-not to mention the savings achieved by extending the resolution of existing capital equipment-far outweigh these factors. Moreover, commercially available tools such as those developed by Numeritech have fully automated the conversion process using fast proprietary algorithms. These tools automatically generate phase shapes, assign phase, identify conflicts, and generate reports without disturbing the data hierarchy of the GDSII. At Motorola, we have exploited the speed of these automated tools to evaluate multiple conversion strategies and ground rule sets on existing layout cells, which helped to optimize parameters and better understand their effects on the design and manufacturability of AAPSMs.

As we mentioned earlier in the article, the relationship between a GDSII file, the related photomask data and the final silicon fundamentally changes in the subwavelength paradigm. Subwavelength distortions cause discrepancies between the files that destroy the WYSIWYG model that worked in the superwavelength paradigm. Unfortunately, today's EDA flow is built around this WYSIWYG model. Use of physical verification tools has traditionally compared a GDSII file against a process' design rules in order to perform a final design rule check (DRC). However, in the subwavelength paradigm, even with strong RET, the GDSII and the end silicon will not match exactly. DRC is checking against an inaccurate model. In the subwavelength realm this can create significant timing discrepancies and design rule violations at the silicon level, which impact yield and reliability.

Take, for example, a basic memory element. Each memory is built up of a large number of bit cells. Each of these bit cells has polysilicon shapes that are pushing against the limits of patterning capability and control and that get slightly distorted with subwavelength manufacturing. Even with RET, silicon does not exactly match the original drawn layout.

As the parasitic capacitance of the bit cells in a word or bit line are all added to the capacitance of this address line, small changes in patterning can significantly compromise the access time specification. In addition, the large number of bit cells in a cache creates a significant yield or reliability impact for rather small shape distortions.

In order to prevent these types of timing violations and yield/reliability detractors, it's important to adequately model the effects of adding RET as a post-layout process. Further, it's important to identify those regions of the design in which the lithographic distortions are significant rather than spurious. Numeritech's SiVL is a simulation tool that models an accurate representation of the silicon that results from a given GDSII file, or given set of photomask data. The tool also flags design violations to enable design fixes.

If SiVL is used on a memory, it will identify areas where the bit cells are printing outside of spec.

Additional RET and OPC features can be used to correct these cells. The end silicon will more closely match the original design intent. The silicon simulation model can then be used as a model for extraction tools to obtain accurate R/C information, which can then be used to accurately recalculate timing. If timing meets specifications, we can release the product-or we can perhaps go back and improve our RET techniques for a more aggressive design specification. This approach allows us to move RET into the heart of the design cycle and to accurately predict our end results before we commit to silicon. For a typical design flow in which back annotation is carried out (not simply from the physical design, but from a virtual post-lithography silicon model), this strategy helps to avoid costly discovery of design issues during production.

Adopting the paradigm

Although using this post-layout simulation and verification method is an effective way to use AAPSM to improve timing of our existing chips, it's not the most efficient method for new designs. Restricting AAPSM to be a post-layout process is a bit like building a house and then attempting to fit a piano through the front door. Without pre-planning, the process is not going to be successful without tearing something apart and reworking it.

However, if bit cells and gates were originally constructed and characterized to account for subwavelength distortions and RET, they would offer accurate R/C and performance models through the synthesis and layout flows. Much of the guardbanding that is done today-and much of the post-layout timing optimization-could be avoided by planning to use RET up-front in the process. Post-layout implementation of RET would then be a much faster process, essentially resulting in a correct by construction design.

In addition, the use of AAPSM-aware library synthesis and place-and-route tools could ensure that phase-conflicts are avoided during library creation and place and route. Because this design approach virtually eliminates post-design rework, it ensures both 'correct-by-construction' design and the optimal benefit from RET throughout the circuit.

As designers and silicon manufacturers, we are forced to provide our systems customers with ever faster, cheaper, and lower-power chips-a demand, which is moving design into the subwavelength realm. At Motorola, we have already applied both OPC and AAPSM enhancements aggressively in our production manufacturing process and have found that using a variety of post-layout tools provides a production-worthy approach for applying RET. However, the availability of these technologies and the emerging subwavelength-design flow place the onus on the designer to take advantage of the strategies in order to remain competitive.