The Co-verification of an RTOS in an SOC
By David Harris, DeVerl Stokes, and Russell Klein

Focus Report: Physical Design
By Mike Maisen and Peggy Aycinena

Feedback
By ISD Staff

Assertion Methodologies for Verilog Design
By Ramesh Sathianathan and Tom Anderson

Internet Changes Office Imaging Requirements
By Beranard Stamme

Reducing Power and Area in Cell-Based Design
By Paul de Dood

The Co-verification of an RTOS in an SOC
By David Harris, DeVerl Stokes, and Russell Klein

Speakers Cite Trouble Spots for SOC, Mobile Designs
By Michael Maisen
By Santa Clara CA - Designers must help solve the power consumption crisis for mobile devices and achieve a better rate of first-pass success with system-on-a-chip (SOC) silicon if those products are to flourish, according to speakers at this week's International Symposium on Quality Electronic Design (ISQED) conference.

Innovation and Stability- Can You Have Both?
By Graham Dodgson

Articulating Hierarchical Design for SOCs
By Jake Buurma

A Few Good Heroes
By Peggy Aycinena

Designers Unite
By Mike Maisen
By Bad times are skulking around, but you must remember the reason to stay inspired. Or, at least I must.

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