Comms SOC Design Challenges Tool Capability
By Bryan Ackland and Eugene Scuteri
By Continuing advances in process technology give us the ability, in principle, to design ever-more-complex communications systems-on-chip at higher speeds.

Physical Design Flow Taps Partition Layout
By Arun Balakrishnan, Gopal Dandu, Wolfgang Roethig and Benny Winefeld
By Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its...

Language Attributes Ensure IC Verification
By Janick Bergeron
By Hardware verification languages (HVLs) have survived past the critical early-adopter stage and are now aggressively entering the mainstream.

FPGA Designs Take on Timing Closures
By Jeff Wilson
By Over the last couple of years, FPGAs have made amazing advances in performance and capacity. Solutions, such as physical synthesis, are now needed that allow designers to take advantage of these improvements.

Rosetta Blooms for System-level Design
By Perry Alexander
By The EDA industry has made significant progress in developing system-level design tools and languages for functional verification.

Interconnect noise models plenty noisy
By Raminderpal Singh
By Looking at today's system-on-chip world, it is easy to concern ourselves with how designers accurately model interconnect noise (glitch and delay) between intellectual-property blocks.

Editorial: Design gap remains, even as ISD fizzles
By Ron Wilson, Editorial Director And Nic Mokhoff, Editor
By Will tools ever exist that can close the design gap? Bryan Ackland, chairman of the 39th Design Automation Conference, being held in New Orleans this month, has his doubts.

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