Researchers at Advanced Micro Devices Inc. last week reported performance gains from a low-aspect-ratio finlike transistor that links three gates surrounding a vertical channel.

Craig Sander, vice president of process technology, said the trigate transistor "is a prime candidate for the 45-nanometer node," which is expected to enter manufacturing four years from now.

If AMD extends its logic process development agreement with IBM Corp. to 45 nm, the two companies could collaboratively develop a vertical-transistor architecture for their respective high-end products, Sander added.

Despite the challenges they present in both design and manufacturing, vertical transistors are cropping up on various technology road maps, in part because of the higher drive current-a function of having more than one gate to turn on the device-and excellent switching speeds seen with the early prototypes. Then too, the vertical transistors can buy time for chip makers, giving them a means of pushing back the transition to a high-k dielectric.

"By using a longer gate and thicker oxide, we can get the performance equivalent of a thinner oxide with a planar transistor," AMD's Sander said. "That means we can back off the gate oxide scaling somewhat."

Intel Corp. and Motorola Inc. also have vertical transistors in development. Indeed, Motorola says it may introduce its version, called the MIGFET, as early as the second stage of the 65-nm node for its PowerPC processors and baseband devices. "If a high-k solution is found, then the industry will continue to push planar technologies for all they are worth," observed Joe Mogab, director of Motorola's Advanced Products Research & Development Lab here. "We are pushing on both, walking a tightrope [between planar and vertical transistors]."

Mark Bohr, senior fellow in charge of process technology development at Intel's logic technology development center in Hillsboro, Ore., reportedly told the Intel Developer Forum last week that some form of multigate device could be used at the 45-nm node. Intel's trigate design uses one horizontal and two vertical sides of the boxlike structure as a connected gate, surrounding a barrel-like channel on three sides.

Mogab said Motorola researchers have devised a vertical transistor with two perfectly aligned but separate gates on each side of the vertical channel. Motorola calls the approach the MIGFET, for multiple-independent-gate field-effect transistor.

Leo Mathew, an engineer in the novel-structures group at the lab who worked on the MIGFET, said that for the first time, Motorola is able to control each gate independently. That opens up the possibility of controlling the threshold voltage of each gate separately, dynamically setting Vt for high drive current or low-power operation.

Both gates could pump current into a pass gate, for example, when designers want to dump as much current as possible through their circuits to improve a part's performance.

Moreover, Motorola engineers believe the approach could halve the number of transistors needed to create logic functions. For conventional planar CMOS, an OR gate requires two NMOS and two PMOS transistors. In the MIGFET architecture, one NMOS and one PMOS transistor are needed, and similar reductions are possible with the other Boolean logic functions, the company said.

Compared with planar CMOS, the MIGFET could improve the ability to shut off the transistors, could eliminate unnecessary interconnects and could reduce parasitic delays, Mathew said.

Zoran Krivokapic, the lead researcher on the multigate project at AMD's technology research group in Sunnyvale, Calif., reported on the company's trigate transistor last week at the International Conference on Solid State Devices and Materials in Tokyo. The transistor switching speed-expressed as CV/I, a measure of capacitance, voltage and current-was 0.26 picosecond for the NMOS devices and 0.45 ps for the PMOS transistors. According to AMD, those are the fastest transistors reported to date for 20-nm gate length structures.

AMD combined several process technology advances in the multigate structure. It used fully silicided metal gates, instead of electrodes made of polysilicon. Rather than deposit the nickel material, AMD used a silicidation process to gradually replace polysilicon with nickel silicide to form the metal gate electrodes.

Also, AMD employed fully depleted silicon-on-insulator (SOI). Combined with the metal gate, the fully depleted SOI creates a strain on the silicon in the channel, which delivers higher-mobility electrons and holes.

Sander said the transistor "demonstrates 50 percent better performance than other multigate devices" discussed in the literature thus far. The stage delay, for example, exceeds the specifications set out by the 2003 International Technology Roadmap for Semiconductors (ITRS) for devices coming to market in the 2009 time frame, he said.

Motorola's Mogab said he is doubtful that a high-k oxide can be ready by the 65-nm node, which is why Motorola is putting more resources into vertical structures. "Conceivably, we could bring in the vertical architecture in the late-2007-ish time frame," he said. AMD's Sander said that if a high-k dielectric becomes available, it could easily be integrated with the vertical transistors, giving them a performance boost as well.

Moving from planar CMOS, first developed at Fairchild Semiconductor in the late 1950s, would entail tremendous changes in semiconductor design and manufacturing, and the economics may delay the transition.

The vertical transistors often require two or three more mask layers than the planar types, said Dean Freeman, a principal analyst at Gartner Dataquest (San Jose, Calif.).

Depending on how the structure is designed, the vertical channel can present a major challenge to lithographers, who must push depth of field in order to make the tall, skinny structures. Sander noted that the AMD structure has a lower aspect ratio than conventional FinFETs, thus easing the lithographic burden.

Etching also is difficult. And most companies will use SOI technology to make vertical transistor structures, in order to reduce leakage current.

Mogab, a Motorola vice president, said the design automation industry would need to adapt its device models and layout tools to the vertical transistors. Motorola has developed, internally, compact models that can be plugged into simulation tools, and Motorola engineer Mathew-a former circuit designer-said the company's MIGFET would be "transparent" to circuit designers once the underlying modeling infrastructure was put in place.

Dan Hutcheson, president of VLSI Research Corp. (San Jose), said he is hearing more-optimistic reports recently concerning high-k gate oxide integration. Samsung and other DRAM vendors are figuring out how to use high-dielectric-constant materials for DRAM capacitors. While the challenges are much different for logic transistors, Hutcheson said he believes the logic vendors are "progressing fairly well" with high-k oxides.

"Intel believes they are ahead in this area, but they don't want to say much about it publicly," Hutcheson said.