Organizers of ISSCC 2003 have arranged a special session that will repeat four presentations first made at the 39th Design Automation Conference (DAC) last June in New Orleans. These papers, on design methodologies and electronic design automation (EDA) tool development, are not typically found at the solid-state circuits conference.

One paper, by Aurangzeb Khan, corporate vice president and general manager of Cadence Design Systems Inc. (Sunnyvale, Calif.), describes the design methodologies and computer-aided design tool requirements for an advanced 10-million-gate SoC in the context of several large design examples.

Another presentation in this special session won DAC's Best Paper award. It describes a novel technique for mixing compiled-code and interpreted-code approaches to instruction set simulation.

The paper, from the Aachen University of Technology in Germany, demonstrates high performance with fewer restrictions than if compile-coding alone is used. The approach is described in the context of several processors, including the ARM7 and ST200.

A third presentation at ISSCC — slated for Feb. 9 to 13 at San Francisco's Marriott Hotel — describes new simulation techniques for fractional-N synthesizers and their application to various circuits. This technique, presented at ISSCC by a researcher from Massachusetts Institute of Technology (Cambridge, Mass.), is especially applicable to system-based wireless communications where frequency synthesizers are critical components.

Spice up analog

The fourth DAC presentation to be repeated at ISSCC is a paper on design-automation techniques for generating high-quality analog performance models, replacing a manual process. The techniques, presented by researchers from Katholieke Universiteit (Leuven, Belgium), are based on a new direct-fitting approach that efficiently fits model templates to numerical data from Spice simulations.

A special session on circuits in emerging technologies — a topic more typical of ISSCC fare — will address techniques for both high-performance design at microwave frequencies and future gigascale integrated circuits. These techniques include high-speed CMOS, silicon germanium, gallium arsenide, indium phosphide, double-gate FinFET and carbon nanotube technologies. One intriguing paper in this session, titled "Integration of Analog, Digital and Power Regulation on a Chip," will be presented by James Mielke, director of systems and architecture at Motorola Inc. (Tempe, Ariz.).

A separate evening session, titled "Analog IP — Stairway to SoC Heaven?" will pose the provocative question of whether new, less-ambitious paradigms can make analog EDA for SoC devices a success. Panelists will include executives from Barcelona Design Inc. (Newark, Calif.), Dolphin Integration (Meylan, France), Hitachi (Gunma-ken, Japan), Philips Semiconductors (U.K.), STMicroelectronics (Crolles, France) and Xignal Technologies (Unterhaching, Germany), and a representative from Katholieke Universiteit.

A panel session organized by K. Nagaraj of Texas Instruments Inc. (Warren, N.J.) promises to be controversial for silicon designers. The session, entitled "SoC: DOA? RIP?" will probe how to integrate RF circuits, including high-quality passives and precision analog circuits, with ultralarge-scale-integration digital circuitry. Issues such as noise coupling and/or MOSFET gate leakages will be contemplated as possible showstoppers for SoC devices. Panelists will be from Analog Devices, IMEC, Intel, Motorola, Stanford University and TI.