Design Con 2015
Breaking News

Curriculum Calendar

Download this to connect our Curriculum Calendar to your calendar application (Outlook, etc.)
All class times are listed in Eastern Time
All classes will consist of a 45 minute lecture and an interactive chat session
Registered users must login to participate and get credit for each course
Questions? Please contact us here.
To suggest a track you would like to see offered, email us at realtimelearning@ubm.com
Intelligent Embedded Systems for the New Era of Industrial Apps  
Monday, November 26 - Friday, November 30
SPONSORED BY
Date Class   Status   Lecturer
Nov 26
12PM
Introduction: Understanding the Connected Factory of the Future & Next-Gen Industrial Apps
In this class, you'll learn how the flexible, digital factory of the future will dominate the industrial arena, what its components are, and how embedded apps are evolving to serve this new environment.
  View Archived  
Brian Bailey  
Brian Bailey is an independent engineering consultant working in the fields of Electronic System Level (ESL) methodologies and ...  
MORE
Our Lecturer
Brian Bailey
Brian Bailey

Brian Bailey is an independent engineering consultant working in the fields of Electronic System Level (ESL) methodologies and functional verification of embedded systems. He was previously chief technologist for verification at Mentor Graphics, where he pioneered work on hardware/software co-design and co-verification. He is the editor for the EETimes Designlines and a contributing editor to EDN. Embedded systems are the point where hardware and software come together, and this is where Brian Bailey has spent most of his working career, first as a tool developer, then as an architect, and later as a technology writer. He has concentrated on the impact that hardware and software can have on each other and the ways in which this is changing over time into the heterogeneous, concurrent, connected applications of today. He has published seven books, given talks around the world, chairs international standards committees, and sits on the technical advisory board for several EDA companies. He graduated from Brunel University in England with a first class honors degree in electrical and electronic engineering.


HIDE
Nov 27
12PM
Part II: Four Pillars of Intelligent Industrial Apps: Security, Manageability, Connectivity & Performance
This lecture will give engineers' perspective about crossing the bridge from the traditional embedded perspective to intelligent applications, which are more adaptive and responsive to user needs throughout their lifecycle. We'll define the four pillars of these apps in the context of both engineering requirements and customer benefits.
  View Archived  
Nov 28
12PM
Part III: Rethinking Embedding Processing: The Bridge to Ivy Bridge
Traditional embedded solutions have drawn from a disparate range of CPU solutions. Emerging, next-gen intelligent apps by definition require a minimum of 32-bits for optimum functionality. We'll dive into the architecture and features of one such family, the third-generation Intel Core vPro Processors, which include multiple x86-64 cores and embedded security.
  View Archived  
Nov 29
12PM
Part IV: Apps Development Utilizing the Partner Ecosystem of Intelligent Solution
To help engineers ensure that end-user specs and constraints are factored into the design equation -- with the output being a reliable, cost-effective end product -- we'll examine the rich ecosystem of boards, operating systems, security solutions, and tools available for building your intelligent app.
  View Archived  
Nov 30
12PM
Part V: Case Study: Highlighting a Successful Design Example
Putting it all together is where the rubber meets the road in any embedded effort. We'll delve into a successful design project, which showcases how engineers at an energy company put to practical use the intelligent concepts discussed in this course to create a noteworthy application.
  View Archived  
All Programmable FPGAs and SoCs for Fast, Cost-Effective Designs  
Monday, December 10 - Friday, December 14
SPONSORED BY
Date Class   Status   Lecturer
Dec 10
12PM
Part I. Introduction: The Basics & Benefits of All Programmable Devices
In this session you will learn about the fundamental lookup table (LUT)-based programmable fabric, along with more sophisticated architectures featuring memory blocks, DSP blocks, and hard and soft processor cores. The various technologies used to create different types of programmable devices -- including antifuse, Flash, and SRAM-based devices -- will be discussed, along with their advantages and disadvantages.
  View Archived  
Max Maxfield  
Max covers programmable logic, microcontroller units, and prototyping for EE Times' Designlines. Over the years, he has designed ...  
MORE
Our Lecturer
Max Maxfield
Max Maxfield

Max covers programmable logic, microcontroller units, and prototyping for EE Times' Designlines. Over the years, he has designed everything from silicon chips to circuit boards, and brainwave amplifiers to steampunk "Display-O-Meters." He has a BSc in Control Engineering in from Sheffield Hallam University in Sheffield, UK.


HIDE
Dec 11
12PM
Part II. Understanding the Role of Hardware Description Languages (HDLs)
In this session, you will be introduced to a number of hardware description languages (HDLs), including Verilog, VHDL, SystemVerilog, and SystemC. The differences between HDLs and traditional programming languages like C/C++ will be discussed, along with the difference in hardware-centric versus software-centric design flows.
  View Archived  
Dec 12
12PM
Part III. Design Tools and Methodologies
In this session, you will learn about the various tools and techniques that may be used to capture All Programmable FPGA and SoC designs. These range from textual descriptions to graphical entry mechanisms, and from hand-coding to high-level synthesis (HLS).
  View Archived  
Dec 13
12PM
Part IV. Programming, Debugging, Verifying & Protecting Designs
In this session, you will discover the various ways in which a design may be loaded into an All Programmable FPGA and/or SoC. Also discussed will be various debugging and verification techniques, along with ways to protect your designs from copying, cloning, overproduction, and other forms of attack.
  View Archived  
Dec 14
12PM
Part V. Advanced Concepts & Future Trends
This final session will cover a wide range of topics, including high-speed serial interconnect, optical interconnect, programmable analog fabric, 3D All Programmable chip technologies, and tools and techniques for creating radiation tolerant All Programmable designs.
  View Archived  
Wireless for Miniaturized Consumer Electronics & Mobile Products  
Monday, January 14 - Friday, January 18
SPONSORED BY
Date Class   Status   Lecturer
Jan 14
12PM
Introduction: Understanding the Different Flavors of IEEE 802.11
Attendees will come away from this EE Times University track with an understanding of the alphabet soup of 802.11 specifications, as well as a brief history of the technology. They'll also learn about mainstream chipsets and reference designs and what's due to emerge in the near future.
  View Archived  
Fanny Mlinarsky  
Fanny Mlinarsky has 28 years of experience developing data communication and test products. As President of octoScope ...  
MORE
Our Lecturer
Fanny Mlinarsky
Fanny Mlinarsky

Fanny Mlinarsky has 28 years of experience developing data communication and test products. As President of octoScope (2006–present) she is responsible for the development of wireless test solutions. From 2001 to 2006 she was founder and CTO of Azimuth Systems, the leading wireless test equipment vendor of WiFi, WiMax, and LTE test systems. As VP of Engineering at Scope Communications (now Agilent), Fanny and her team developed network test equipment (1993–2001). She has published more than 50 articles and whitepapers on wireless technologies and standards and is a frequent presenter at industry conferences. She actively participates in industry standards development at IEEE and 3GPP.


HIDE
Jan 15
12PM
Part II: MIMO or SISO? Wireless Board Design Considerations & Trade-Offs
This class will discuss the basics of MIMO radio technology, present real-life measurements of MIMO versus SISO performance, and discuss the cost/performance/power consumption trade-offs of different design approaches.
  View Archived  
Jan 16
12PM
Part III: Bluetooth
Today's lecture will cover the evolution of Bluetooth, including Bluetooth 3.0 and 4.0; give an overview the Bluetooth protocol and standards; and examine the capabilities of available devices.
  View Archived  
Jan 17
12PM
Part IV: Standards-Based vs. Proprietary Wireless Implementations
In this lecture, we'll learn about proprietary wireless solutions and tradeoffs of proprietary versus standards-based radio design for a variety of applications.
  View Archived  
Jan 18
12PM
Part V: Challenges of RF Test, Integration & Compliance in the Final Product
Today's session will cover industry-accepted test methods and metrics at different stages of product lifecycle, including R&D, certification, QA, production, and field testing.
  View Archived  
Bringing Intelligence Into Industrial Systems  
Monday, August 19 - Friday, August 23
SPONSORED BY
Date Class   Status   Lecturer
Aug 19
12PM
Part I: Introduction: Pervasive Change
In this class we will look at the broad scope of the changes happening in many segments of the industry, including the cloud, autonomous cars, factory automation, the smart grid, and others. It will look at the ways embedded systems are changing and what is meant by "intelligent" systems. We will identify the major pieces of these systems and some of the issues they create.
  View Archived  
Brian Bailey  
Brian Bailey is an independent engineering consultant working in the fields of Electronic System Level (ESL) methodologies and ...  
MORE
Our Lecturer
Brian Bailey
Brian Bailey

Brian Bailey is an independent engineering consultant working in the fields of Electronic System Level (ESL) methodologies and functional verification of embedded systems. He was previously chief technologist for verification at Mentor Graphics, where he pioneered work on hardware/software co-design and co-verification. He is the editor for the EETimes Designlines and a contributing editor to EDN. Embedded systems are the point where hardware and software come together, and this is where Brian Bailey has spent most of his working career, first as a tool developer, then as an architect, and later as a technology writer. He has concentrated on the impact that hardware and software can have on each other and the ways in which this is changing over time into the heterogeneous, concurrent, connected applications of today. He has published seven books, given talks around the world, chairs international standards committees, and sits on the technical advisory board for several EDA companies. He graduated from Brunel University in England with a first class honors degree in electrical and electronic engineering.


HIDE
Aug 20
12PM
Part II: Consolidation
In this class we will look at what is happening in the compute centers and, in particular, technologies such as multicore and virtualization. Consolidation enables more efficient computing, centralized management, integrated data management, and visualization, as well as enabling new types of applications and automation in industrial systems.
  View Archived  
Aug 21
12PM
Part III: Security
As sensors become distributed and data is collected from diverse sources, the systems become more vulnerable to attack. What can be done to ensure that both the data and the integrity of the system remain secure from internal and external attacks? In this segment we will look at both hardware and software techniques to secure the system.
  View Archived  
Aug 22
12PM
Part IV: Getting Lost in the Data
With so much data becoming available, it can affect the way systems are designed and software is written. In this class we will look at some of the tradeoffs among compressing, encrypting, and transmitting data across a network, particularly in systems where power is a scarce resource.
  View Archived  
Aug 23
12PM
Part V: Case Study
In this final class, we will consider how a modification in the supply chain can change the way an industrial system is designed, deployed, and maintained. Specifically, we will take a look at the industrial embedded computer business of Dellís OEM division and how a change in infrastructure can impact the whole industry.
  View Archived  
Busting the HighSpeed Digital Design Roadblock  
Monday, September 9 - Friday, September 13
SPONSORED BY
Date Class   Status   Lecturer
Sep 9
12PM
Part I: Introduction to Digital Signal Integrity at High Data Rates
  • High-speed serial-data systems
  • Differential signaling
  • Embedded clocking
  View Archived  
Ransom Stephens  
Ransom Stephens is a technologist, science writer, novelist, and Raiders fan.  
MORE
Our Lecturer
Ransom Stephens
Ransom Stephens

Ransom Stephens is a technologistscience writernovelist, and Raiders fan.


HIDE
Sep 10
12PM
Part II: Signal Integrity & the Closed Eye
  • The digital myth and analog reality
  • Dispersion, skin effect, and inter-symbol interference
  • Noise and jitter
  • Crosstalk
  View Archived  
Sep 11
12PM
Part III: Total Jitter & Eye Width
  • In search of peak-to-peak jitter
  • Total jitter at a bit error ratio
  • The dual-Dirac Model
  • Combining component jitter to estimate system jitter
  • Measuring and estimating TJ(BER)
  View Archived  
Sep 12
12PM
Part IV: Opening Closed Eye Diagrams
  • Pre/de-emphasis
  • Equalization techniques
  • CTLE, FFE, DFE, and adaptive equalization
  • Equalization problems with crosstalk
  View Archived  
Sep 13
12PM
Part V: High-Speed Standards Compliance & Diagnostic Testing
  • Overview HSS standards: PCIe, OIF-CEI, 32G FibreChannel, 100 Gb Ethernet
  • Eye diagrams and transmitter testing
  • Channel, interconnect, and backplane testing
  • Receiver tolerance testing
  • Looking forward: 400G, 1T, more channels, more challenges. Super-Channel!
  View Archived  
Fundamentals of Microcontrollers (MCUs): Hands-On Workshop  
Monday, December 2 - Friday, December 13
SPONSORED BY
Date Class   Status   Lecturer
Dec 2
12PM
Session 1 - Introduction to Microcontrollers*
  • Introduction to microcontrollers
  • Common microcontroller architectures
  • Pipelining
  • Peripherals
    • Timers
    • Communication
    • Analog
*The first 1,000 qualified attendees of Day 1 & 2 (US or Canada- attended by 12/3 5pm PST) will receive a Free STM32F429 Discovery Board for the hands-on workshop Days 3-5.
  View Archived  
Jacob Beningo  
Jacob Beningo is a Certified Software Development Professional (CSDP) and lecturer who specializes in the design of reusable and ...  
MORE
Our Lecturer
Jacob Beningo
Jacob Beningo

Jacob Beningo is a Certified Software Development Professional (CSDP) and lecturer who specializes in the design of reusable and configurable embedded software. He has successfully completed projects across a number of industries including automotive, defense, medical, and space. He enjoys developing and teaching real-time and event-driven software using the latest techniques and tools. He is an avid tweeter, a tip and trick guru, a homebrew connoisseur, and a fan of pineapple! Jacob holds Bachelor's degrees in electrical engineering, physics, and mathematics from Central Michigan University and a Master's degree in space systems engineering from the University of Michigan.


HIDE
Dec 3
12PM
Session 2 - Selecting the Right Microcontroller*
  • 10 Steps to Selecting a microcontroller
  • What to look for in a development kit
  • Tool setup lab
*The first 1,000 qualified attendees of Day 1 & 2 (US or Canada- attended by 12/3 5pm PST) will receive a Free STM32F429 Discovery Board for the hands-on workshop Days 3-5.
  View Archived  
Dec 11
12PM
Session 3 - An Overview of the STM32F4 Discovery Board (Hands-On Workshop)
  • Overview of the STM32F4
  • The ST family of microcontrollers
  • Ecosystem
  • Peripheral set
    • Graphics
    • DSP
    • Low power modes
  • Onboard sensors
    • Gyro, etc.
  • Expansion
  • Toolchain setup
  • MicoXplorer
  View Archived  
Dec 12
12PM
Session 4 - Digital Signal Processing With the STM32F4 (Hands-On Workshop)
  • Introduction to DSP
  • DSP features
  • DSP instructions
  • Floating point
  • DSP example
  View Archived  
Dec 13
12PM
Session 5 - Introduction to Graphics Processing (Hands-On Workshop)
  • Introduction to graphics processing
  • Graphics peripheral
  • Graphics toolchain
  • Example
  View Archived  
A Vector Network Analyzer Manifesto: A Primer for Practical Mastery  
Monday, January 20 - Friday, January 24
SPONSORED BY
Date Class   Status   Lecturer
Jan 20
12PM
Day 1: What Is an S-Parameter?
  • Review of basic S-parameter theory
  • Intuitive interpretation of S-parameters
  • Vector relationship of S11 on S21
  • What is a decent S11 versus a max frequency of interest?
  • Establishing port definitions cleanly for RF versus 3D EM/Signal Integrity
  • Transforming S-parameters into the time domain - primer of problems, things to look out for
  View Archived  
Alfred Neves  
Alfred Neves, Chief Technologist and Founder of Wild River Technology, has 33 years of experience in the design and application ...  
MORE
Our Lecturer
Alfred Neves
Alfred Neves

Alfred Neves, Chief Technologist and Founder of Wild River Technology, has 33 years of experience in the design and application development of semiconductor products and capital equipment design focused on jitter and signal integrity analysis. He is involved with the signal integrity community as a consultant, high-speed system-level design manager, and engineer. Recent technical accomplishments include development of platforms to improve 3D electromagnetic correspondence to measure-based methods. Neves earned a Bachelor's degree in applied mathematics at the University of Massachusetts.


HIDE
Jan 21
12PM
Day 2: What Is a VNA & How Does It Work?
  • Structure of a VNA, block diagrams and function
  • Reference plane and error box concept
  • Anatomy of a SOLT calibration
  • Overview of mechanical and electronic calibrations, dispelling some popular misconceptions
  View Archived  
Jan 22
12PM
Day 3: What Constitutes a 'Good' VNA Measurement?
  • Calibration validation scope
  • How device under test impacts your measurement error
  • Tips and approaches for dealing with bad calibrations
  • Measurement work flow - the process of good S-parameter measurement
  • Exploiting device geometries and relating them to the S-parameter matrix
  • Simple passivity and causality checks using Matlab
  • and much more
  View Archived  
Jan 23
12PM
Day 4: Application Topics of S-Parameters
  • Rational expansion of the S-parameter - why do it, how
  • Selecting a VNA, features and function relevant to signal integrity
  • Third-party tools we use in our S-parameter measurement flow
  • Compliance application - 10G-KR, 10 Gbit/s backplane analysis, what is involved
  View Archived  
Jan 24
12PM
Day 5: Application & Case Examples
  • Comparison of two VIAs
  • T-line loss
  • Differential mode analysis
  • Time-domain transform resonator with and without gating
  • Wrap-up
  View Archived