It's usually said multipatterning costs will be prohibitively high, and that's why companies want to avoid it. The cost barrier is said to slow down Moore's Law. Ironically, the real reason to fear multipatterning is it would force us to speed the shrink rate. For simple discussion's sake, let's assume double patterning is twice as expensive as single patterning. If I do a shrink from 90 nm pitch to 63 nm pitch with DP, I haven't realized a reduction of cost per bit or per transistor, even though I advanced one node with 70% scaling, because cost is doubled along with the number of transistors in the chip. However, if I went faster than Moore, and scaled 60% to 54 nm pitch instead, though I doubled costs, area scaled down to 36%, so chip price is scaled down to 72%. It is a definite reduction of chip cost, but not the proverbial 50%. But following this path would mean 45,27,16,10,6 nm node scaling instead of 45,32,22,15,11,8,6 nm traditional Moore scaling, so it's shrinking devices much faster. Can companies take the added pressure for both device and process development? Hard to think so.