@lleiva: "the synthesis from C/C+ is effective in terms of time and area? "
The big advantage of HLS (sythesis from C/C ) is that it allows you to explore lots of different implementation options -- you can make something very area effcients (by resource sharing) but have lower performance, or use a lot of area (resources in FPGA terms) and have higher performance -- like all engineering it's a tradeoff
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.