In today's lecture, it was a bit unclear to me regarding slides 4, 5, 6 ... and later slide 12. I agree what was said regarding slide 4 -- that at the end of execution, both registers will contain the value 6. However, it appears to me that this is NOT the case for slide 5 with common clock (seems that registers will swap values with each clock cycle). And what about slide 6 ... depends on whether the last 2 instructions are executed sequentially or concurrently ? Similarly, for slide 12 (& slide 13). With a common clock, what happens to blocks B, C, & D during the first 3 clock cycles until the pipeline is "loaded". Are we to assign some initial conditions to the appropriate registers (during power-on-reset or equivalent) such that whatever values reside on the output registers are loaded into the successive register -- until the first 4 clock cycles are finally achieved ? I am an analog engineer, dabbling here. Thanks.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.