In today's lecture, it was a bit unclear to me regarding slides 4, 5, 6 ... and later slide 12. I agree what was said regarding slide 4 -- that at the end of execution, both registers will contain the value 6. However, it appears to me that this is NOT the case for slide 5 with common clock (seems that registers will swap values with each clock cycle). And what about slide 6 ... depends on whether the last 2 instructions are executed sequentially or concurrently ? Similarly, for slide 12 (& slide 13). With a common clock, what happens to blocks B, C, & D during the first 3 clock cycles until the pipeline is "loaded". Are we to assign some initial conditions to the appropriate registers (during power-on-reset or equivalent) such that whatever values reside on the output registers are loaded into the successive register -- until the first 4 clock cycles are finally achieved ? I am an analog engineer, dabbling here. Thanks.
NASA's Orion Flight Software Production Systems Manager Darrel G. Raines joins Planet Analog Editor Steve Taranovich and Embedded.com Editor Max Maxfield to talk about embedded flight software used in Orion Spacecraft, part of NASA's Mars mission. Live radio show and live chat. Get your questions ready.
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