Personally I find SystemVerilog quite comfortable to work with (my experience is mostly with synthesis, rather than verification). It has enough support for low-level stuff (down to the transistor level) and high-level abstractions (even structured data types and object orientation). Add to that general industry support (and investment) and you have a clear winner. I see the subject of Verilog vs. VHDL in the same way as the old C vs. Pascal conflict from the 80s.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.