HLS refers to a form of synthesis technology, RTL refers to a level of design abstraction. HLS takes a C/C+ description and generates RTL (in the form of Verilog or VHDL) -- thsi RTL is then "consumed" by regular logic synthesis
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.