@Ash88: Which one is getting more attention to enhance and improve and which one do you think will dominate :)
Historically there's been an inertic when it comes to moving forward. When Verilog and VHDL an dSynthesis firtst came out, designers said that they could create better designs by hand working at the gate level. But that's only true when you are working with a limited numbert of gates. When you are deallling with 100,000+ gates, you can experiment with your RTL and synthesise it much quicker.
Now we have C/C== and HLS (which as I say is used to generate VHDL/Verilog and output) -- some people a reluctant to use it, but others are using it to create really REALLY big designs...
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