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Bill T
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Re: Part III. Design Tools and Methodologies
Bill T   12/12/2012 12:31:09 PM
NO RATINGS
Our SoC/ASIC is targeted at a high performance electromechanical storage device for highly cost-competitive markets. The design is fairly stable so there is no need for the experimentation which an FPGA would provide and the FPGA is too costly in performance and dollars to include in mass production. But our early prototypes did use FPGA's.



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