REGISTER | LOGIN
Breaking News
Comment
Dave Callaghan
User Rank
Author
Re: Part III. Design Tools and Methodologies
Dave Callaghan   12/12/2012 12:47:34 PM
NO RATINGS
You are forced to specify you design at system level. There are some annoying restrictions but if you insist you can edit the compiled HDL code in Verilog or VHDL before synthesis.



Like Us on Facebook